ZL50070GAC ZARLINK [Zarlink Semiconductor Inc], ZL50070GAC Datasheet - Page 21

• Manufacturer Part Number: ZL50070GAC
• Description: 24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 96 Inputs and 96 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

By default all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output
frame boundary (assuming ST-BUS formatting). The output advancement is enabled by the Output Stream Bit
Advancement (bits 21 - 20) of the Group Control Registers 0 - 23 (GCR0 - 23), as described in Section 14.4. The
output delay can vary from 0 to 22.8 ns with a 7.6 ns increment. The exception to this is output streams
programmed at 65 Mbps, in which case the increment is 3.8 ns with a total advancement of 11.4 ns.
This programming feature is provided to assist in designs where per stream routing delays are significant and
different.
The OSBA bits in the Group Control Registers are used to set the bit-advancement for each of the corresponding
serial output stream groups. Figure 6 illustrates the effect of the OSBA settings on the output timing.
There are limitations when the ZL50070 is programmed to use CKi2 - 0 as the output stream clock source:
•
•
If the selected reference clock frequency is 65 MHz or 32 MHz, the granularity of the advancement is
reduced to 1/2 the clock period
If the selected reference clock frequency is 16 MHz or 8 MHz, bit advancement is not available and the
output streams are driven at the nominal times
Nominal 8 MHz
Clock
Nominal 16 MHz
Clock
Nominal 32/65 MHz
Clock
Nominal Output
Bit Timing
Level 1
Advance
Level 2
Advance
Level 3
Advance
OSBA = 00
OSBA = 01
OSBA = 10
OSBA = 11
Figure 6 - Output Bit Advancement Timing
Zarlink Semiconductor Inc.
ZL50070
21
7.6 ns (~3.8 ns at 65 Mbps)
15.2 ns (~7.6 ns at 65 Mbps)
22.8 ns (~11.4 ns at 65 Mbps)
Data Sheet