ZL50073GAC ZARLINK [Zarlink Semiconductor Inc], ZL50073GAC Datasheet - Page 26

• Manufacturer Part Number: ZL50073GAC
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps)
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

10.2
In 32 bit mode (D16B = 0), all 32 bits of the Data Bus, D31 - 0, may be used for write and read transfers. D31 on the
bus maps to Bit 31 of the internal memory or register, D30 maps to Bit 30, etc. The least significant address bits, A1
- 0, and the Data Transfer Size inputs, SIZ0 - 1, identify which bytes are being accessed.
In Motorola Bus mode (IM = 0), A1 - 0 identify the first byte in the 32 bit field to be transferred, as shown in Table 6.
The SIZ0 - 1 inputs indicate the access transfer size, as shown in Table 7.
For example, to transfer all 32 bits in a single access: A1 = 0. A0 = 0, SIZ1 = 0, SIZ0 = 0. To transfer D15 - 8 only:
A1 = 1, A0 = 0, SIZ1 = 0, SIZ0 = 1.
In Intel Bus Mode (IM = 1), A1 - 0, and SIZ1 - 0 form active low byte enable signals, consistent with BE3 - 0
available on the Intel i960 processor, as shown in Table 8.
Byte addressing applies only to write accesses. On read cycles, all 32 bits are output on every access.
32 bit Bus Operation
Table 7 - 32 Bit Motorola Mode Access Transfer Size
Table 5 - Example of Address and Byte Significance
Address (Hex)
SIZ1
Table 6 - 32 Bit Motorola Mode Byte Addressing
Table 8 - 32 bit Intel Mode Bus Enable Signals
0
0
1
1
40200
40201
40202
40203
A1
SIZ1
SIZ0
0
0
1
1
Pin
A1
A0
SIZ0
0
1
0
1
Zarlink Semiconductor Inc.
A0
0
1
0
1
ZL50073
i960 Signal
Equivalent
26
BE3
BE2
BE1
BE0
Access Transfer Size
Memory/Register Bits
Byte Addressed
Bits 31:24 (MSB)
Bits 7:0 (LSB)
Bit 31:24
Bit 23:16
Bits 23:16
Bit 15:8
4 Bytes
2 Bytes
3 Bytes
Bits 15:8
Bit 7:0
1 Byte
Addressed
Bit 31:24
Bit 23:16
Bit 15:8
Bit 7:0
Byte
Data Sheet