ZL50073GAC ZARLINK [Zarlink Semiconductor Inc], ZL50073GAC Datasheet - Page 36
ZL50073GAC
Manufacturer Part Number
ZL50073GAC
Description
32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps)
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50073GAC.pdf
(67 pages)
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27 - 26
25 - 24
23 - 15
14 - 10
PCF
External Read/Write Address: 000000
Reset Value: 0000
31
15
Bit
28
2
0
PCF
GP
30
14
1
4
OCL1 - 0
ICL1 - 0
Unused
GP4 - 0
Name
V/D
PCF
GP
29
13
0
3
H
V/D
GP
28
12
2
Voice/Data Control
When this bit is low, the corresponding channel is for voice.
When this bit is high, the corresponding channel is for data.
Input Coding Law
Output Coding Law
Reserved. In normal functional mode, these bits MUST be set to zero.
Source Group Selection. These bits define the input/source group number (31 - 0).
Table 16 - Connection Memory Bits (CMB) (continued)
ICL
GP
27
11
1
1
OCL1 - 0
ICL1 - 0
H
00
01
10
00
01
10
11
11
ICL
GP
26
10
0
0
STCH
OCL
25
1
9
9
Zarlink Semiconductor Inc.
STCH
OCL
ZL50073
24
0
8
8
For Voice (V/D bit = 0)
For Voice (V/D bit = 0)
µ-Law w/o Mag. Inv
µ-Law w/o Mag. Inv
CCITT.ITU A-Law
CCITT.ITU A-Law
CCITT.ITU µ-Law
CCITT.ITU µ-Law
A-Law w/o ABI
A-Law w/o ABI
36
STCH
23
7
0
7
Description
STCH
22
0
6
6
Output Coding Law
Input Coding Law
STCH
21
5
0
5
STCH
20
0
4
4
For Data (V/D bit = 1)
For Data (V/D bit = 1)
STCH
All Bits Inverted
All Bits Inverted
19
3
0
3
Inverted ABI
Inverted ABI
No Code
No Code
ABI
ABI
STCH
18
0
2
2
Data Sheet
STCH
17
1
0
1
STCH
16
0
0
0
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