AM79C984AKCW AMD [Advanced Micro Devices], AM79C984AKCW Datasheet - Page 18

• Manufacturer Part Number: AM79C984AKCW
• Manufacturer: AMD [Advanced Micro Devices]

Notes:
1. CRS = Carrier Sense, COL = Collision, JAB = Jabber, LINK = Link, LB = Loop Back, PAR = Partition, DIS = Port Disabled,
2. For the LDC
3. All LEDs blink 16 times at 260 ms per blink after reset.
4. All LEDs are on for approximately 4 seconds after reset.
5. LDC
LED software override is executed in two stages, by
first issuing the blink rate (Software Override of LED
Blink Rate) and then issuing the command to enable
the particular port LEDs (Enable Software Override of
Bank
software override control will reference the blink rate
last issued by the Software Override of the LED Blink
Rate command.
LDA
put drivers that sink 12 mA of current to turn on the
LEDs. In a multiple eIMR configuration, the outputs
from the global LED drivers (LDGA and LDGB) of each
chip can be tied together to drive a single pair of global
status LEDs.
CRS and COL are extended to make it easier for visual
recognition; that is, they will remain active for some
time even if the corresponding condition has expired.
Once carrier sense is active, CRS will remain active for
a minimum of 4 ms. Once a collision is detected, COL
is active for at least 4 ms. The exception to this rule is
for selection LDC
stretched to 100 s.
When LDC
tribute (LB) for the AUI port is displayed on LDA
true when DO on the MAU is successfully looped back
to DI on the AUI port. LB is false (off) if a loopback error
is detected, or if the AUI port is disabled or in the re-
verse mode. Transmit carrier sense is sampled at the
end of packet to determine the state of LB. The state of
LB remains latched until carrier sense is sampled again
for the next packet. The default/power-up state for LB is
false (off).
18
LDC
blk = Blink (Number = period of Blink).
0
0
0
0
1
1
1
1
0-4
LED Control
2
, LDB
0-2
A/B LEDs). All port combinations selected for
LDC
0
0
1
1
0
0
1
1
= ‘010’ and ‘011’ are undefined.
0-2
1
0-4
0-2
= 000 or LDC
LDC
, LDGA, and LDGB are open drain out-
0
1
0
1
0
1
0
1
setting of 000: If the port is partitioned, the LINK LED is off.
0-2
0
= 111. For this selection, COL is
CRS 260-ms blk
LDGA
CRS
CRS
COL
CRS
CRS
0-2
Table 2. LED Attribute-Monitoring Program Options
Global LEDs
= 001, the loopback at-
COL 260-ms blk
LDGB
COL
COL
COL
COL
JAB
P R E L I M I N A R Y
0
. LB is
Am79C984A
CRS 260-ms blk
CRS 512-ms blk
CRS 130-ms blk
PAR 1.56-s blk
LINK (Note 2)
LINK (Note 3)
LINK (Note 4)
LDA
LINK
LINK
LINK
Reserved (Note 5)
Reserved (Note 5)
Figure 1 shows the recommended connection of LEDs.
When LDA
LED lights.
Network Activity Display
The eIMR status port can drive up to eight LEDs to in-
dicate the network-utilization level as a percentage of
bandwidth. The status port uses eight dedicated out-
puts (ACT
LEDs in the series that will be lit increases as the
amount of network activity increases. ACT
the lowest level of activity; ACT
est. ACT
12 mA of current to turn on the LEDs. See Figure 2.
1-4
Figure 1. Visual Monitoring Application—Direct
TP LEDs
COL 260-ms blk
eIMR
LED
Interface
0-7
PAR (Note 3)
COL (Note 4)
0-7
PAR or DIS
0-4
LDA[4:0]
LDB[4:0]
LDB
are open-drain outputs that typically sink
) to drive a series of LEDs. The number of
CRS
PAR
PAR
, LDB
LDGA
LDGB
1-4
0-4
LED Drive
, LDGA, or LDGB are LOW, the
CRS 260-ms blk
CRS 512-ms blk
CRS 130-ms blk
PAR 1.56-s blk
(Note 3)
(Note 4)
LDA
LB
LB
7
0
V
represents the high-
DD
AUI LEDs
R
Typical
20650B-6
20650A-6
COL 260-ms blk
PAR (Note 3)
PAR (Note 4)
0
PAR or DIS
represents
LDB
PAR
CRS
PAR
0