AM79C985KCW AMD [Advanced Micro Devices], AM79C985KCW Datasheet - Page 14

• Manufacturer Part Number: AM79C985KCW
• Manufacturer: AMD [Advanced Micro Devices]

LED Interface
LDA
LED Drivers
Output, Open Drain
LDA
respectively. LDA
AUI port; LDA
four TP ports. The port attributes monitored by LDA
and LDB
LDGA
Global LED Driver, Bank A
Output, Open Drain
LDGA is the Global LED driver for LED Bank A. The
signal represents global CRS or COL conditions. In a
multiple-eIMR+ configuration, LDGA from each of the
eIMR+ devices can be tied together to drive a single
global LED in Bank A.
LDGB
Global LED Driver, Bank B
Output, Open Drain
LDGB is the Global LED driver for LED Bank B. The
signal represents global CRS or JAB conditions. In a
multiple eIMR+ configuration, LDGB from each of the
eIMR+ devices can be tied together to drive a single
global LED in Bank B.
LDC
LED Control
Input
These pins select the attributes that will be displayed
on LDA
grammed to display two attributes, the attribute associ-
ated with the periodic blink takes precedence.
ACT
Activity Display
Output, Open Drain
These signals drive the activity LEDs, which indicate
the percentage of network utilization. The display is up-
dated every 250 ms.
14
0-4
0-4
0-7
0-2
, LDB
and LDB
0-4
0-4
, LDB
are programmed by three pins, LDC
0-4
1-4
0-4
0-4
0
and LDB
, LDGA, and LDGB. If an LED is pro-
and LDB
drive LED Bank A and LED Bank B,
1-4
0
indicate the status of the
indicate the status of the
P R E L I M I N A R Y
0-2
.
Am79C985
0-4
Miscellaneous Pins
RST
Reset
Input, Active LOW
When RST is LOW, the eIMR+ device resets to its de-
fault state. On the rising (trailing) edge of RST, the
eIMR+ also monitors the state of the SELI
AMODE pins, to configure the operating mode of the
device. In multiple eIMR+ systems, the falling (leading)
edge of the RST signal must be synchronized to CLK.
CLK
Master Clock In
Input
This pin is a 20-MHz clock input.
REXT
External Reference
Input
This pin is used for an internal current reference. It must
be tied to VDD via a 13-k resistor with 1% tolerance.
VDD
Power
Power Pin
This pin supplies power to the device.
AVSS
Analog Ground
Ground Pin
This pin is the ground reference for the differential
receivers and drivers.
DVSS
Digital Ground
Ground Pin
This pin is the ground reference for all the digital logic
in the eIMR+ device.
0-1
, SI, and