AM79C985KCW AMD [Advanced Micro Devices], AM79C985KCW Datasheet - Page 37

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AM79C985KCW

Manufacturer Part Number
AM79C985KCW
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
SWITCHING CHARACTERISTICS
AUI Port Timing
Expansion Bus Timing
Clock and Reset Timing
Parameter
t
Symbol
t
t
t
t
t
t
t
SCLKHLD
t
CLKHRH
CLKHDR
t
RSTSET
RSTHLD
t
t
t
t
CLKHRL
CLKHDZ
DJHOLD
t
t
t
t
t
DOETD
t
t
t
t
t
PWODI
PWKDI
PWOCI
PWKCI
t
CASET
CAHLD
t
DJSET
DORM
t
t
t
t
DOTD
DOTR
t
CLKH
CLKR
PRST
t
DOTF
CLKL
CLKF
CIRM
CITR
CITF
XRS
XRH
CLK
RST
CLK Clock Period
CLK Clock High
CLK Clock Low
CLK Rise Time
CLK Fall Time
Reset Pulse Width after Power On
Reset Pulse Width
Reset HIGH Setup Time with respect to CLK
Reset LOW Hold Time
AMODE, SELI
Time to Rising Edge of RST
AMODE,SELI
from Rising Edge of RST
CLK Rising Edge to DO Toggle
DO+, DO– Rise Time (10% to 90%)
DO+, DO– Fall Time (90% to 10%)
DO+, DO– Rise and Fall Time Mismatch
DO End of Transmission
DI Pulse Width Accept/Reject Threshold
DI Pulse Width Not to Turn-off Internal
Carrier Sense
CI Pulse Width Accept/Reject Threshold
CI Pulse Width Not to Turn-off Threshold
CI Rise Time (In Reverse Mode)
CI Fall Time (In Reverse Mode)
CI+, CI– Rise and Fall Time Mismatch
(AUI in Reverse Mode)
CLK HIGH to SELO Driven LOW
CLK HIGH to SELO Driven HIGH
CLK HIGH to DAT/JAM Driven
CLK HIGH to DAT/JAM Not Driven
DAT/JAM Setup Time to CLK
DAT/JAM Hold Time from CLK
COL/ACK Setup Time to CLK
COL/ACK Hold Time from CLK
SI, SCLK Hold Time
Parameter Description
0
0
, CRS_I and SI_D Hold Time
, CRS_I, and SI_D Setup
P R E L I M I N A R Y
Am79C985
|V
|V
|V
|V
Test Conditions
IN
IN
IN
IN
|>|V
|>|V
|>|V
|>|V
C
C
C
C
L
L
L
L
= 100 pF
= 100 pF
ASQ
ASQ
ASQ
ASQ
= 50 pF
= 50 pF
| (Note 2)
| (Note 3)
| (Note 4)
| (Note 5)
49.995
Min
150
400
275
136
20
20
15
15
10
75
15
15
14
14
10
10
50
4
0
0
9
9
50.005
Max
375
200
160
7.0
7.0
1.0
7.0
7.0
1.0
30
30
10
10
30
45
26
30
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
37

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