AM79C985KCW AMD [Advanced Micro Devices], AM79C985KCW Datasheet - Page 18

• Manufacturer Part Number: AM79C985KCW
• Manufacturer: AMD [Advanced Micro Devices]

Notes:
1. CRS = Carrier Sense, COL = Collision, JAB = Jabber, LINK = Link, LB = Loop Back, PAR = Partition, DIS = Port Disabled,
2. For the LDC
3. All LEDs blink 16 times at 260 ms per blink after reset.
4. All LEDs are on for approximately 4 seconds after reset.
5. LDC
The LEDs can also be controlled via the management
port. The Enable Software Override commands turn
the LEDs on regardless of the attributes selected for
display through the LDC setting. Enable Software
Override of Bank A LEDs causes the LDA
pins to be driven LOW, and Enable Software Override
of Bank B LEDs causes the LDB
be driven LOW. The blink rate is set by the Software
Override LED Blink Rate command. The periods are
off, 512 ms, 1560 ms, or solid on.
LED software override is executed in two stages, by
first issuing the blink rate (Software Override of LED
Blink Rate) and then issuing the command to enable
the particular port LEDs (Enable Software Override of
Bank
software override control will reference the blink rate
last issued by the Software Override of the LED Blink
Rate command.
LDA
put drivers that sink 12 mA of current to turn on the
LEDs. In a multiple eIMR+ configuration, the outputs
from the global LED drivers (LDGA and LDGB) of each
chip can be tied together to drive a single pair of global
status LEDs.
CRS and COL are extended to make it easier for visual
recognition; that is, they will remain active for some
time even if the corresponding condition has expired.
Once carrier sense is active, CRS will remain active for
a minimum of 4 ms. Once a collision is detected, COL
is active for at least 4 ms. The exception to this rule is
for selection LDC
stretched to 100 s.
18
LDC
blk = Blink (Number = period of Blink).
0
0
0
0
1
1
1
1
0-4
LED Control
2
, LDB
0-2
A/B LEDs). All port combinations selected for
LDC
0
0
1
1
0
0
1
1
= ‘010’ and ‘011’ are undefined.
1
0-4
0-2
LDC
, LDGA, and LDGB are open drain out-
0
1
0
1
0
1
0
1
setting of 000: If the port is partitioned, the LINK LED is off.
0-2
0
= 111. For this selection, COL is
CRS 260-ms blk
LDGA
CRS
CRS
COL
CRS
CRS
Table 2. LED Attribute-Monitoring Program Options
Global LEDs
0-4
and LDGB pins to
COL 260-ms blk
0-4
LDGB
COL
COL
COL
COL
JAB
P R E L I M I N A R Y
and LDGA
Am79C985
CRS 260-ms blk
CRS 512-ms blk
CRS 130-ms blk
PAR 1.56-s blk
LINK (Note 2)
LINK (Note 3)
LINK (Note 4)
LDA
LINK
LINK
LINK
When LDC
tribute (LB) for the AUI port is displayed on LDA
true when DO on the MAU is successfully looped back
to DI on the AUI port. LB is false (off) if a loopback error
is detected, or if the AUI port is disabled or in the re-
verse mode. Transmit carrier sense is sampled at the
end of packet to determine the state of LB. The state of
LB remains latched until carrier sense is sampled again
for the next packet. The default/power-up state for LB is
false (off).
Figure 1 shows the recommended connection of LEDs.
When LDA
LED lights.
Reserved (Note 5)
Reserved (Note 5)
1-4
Figure 1. Visual Monitoring Application—Direct
TP LEDs
eIMR+
LED
Interface
COL 260-ms blk
PAR (Note 3)
COL (Note 4)
LDA[4:0]
LDB[4:0]
PAR or DIS
0-4
0-2
LDB
LDGA
LDGB
, LDB
CRS
PAR
PAR
= 000 or LDC
1-4
0-4
LED Drive
, LDGA, or LDGB are LOW, the
CRS 260-ms blk
CRS 512-ms blk
CRS 130-ms blk
PAR 1.56-s blk
0-2
(Note 3)
(Note 4)
LDA
LB
LB
= 001, the loopback at-
V
DD
0
AUI LEDs
20651B-6
R
Typical
20651A-6
COL 260-ms blk
PAR (Note 3)
PAR (Note 4)
PAR or DIS
LDB
PAR
CRS
PAR
0
. LB is
0