ZL50130PBGA ZARLINK [Zarlink Semiconductor Inc], ZL50130PBGA Datasheet - Page 10

• Manufacturer Part Number: ZL50130PBGA
• Description: Ethernet Pseudo-Wires across a PSN
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

ZL50130 Package view from TOP side. Note that ball A1 is non-chamfered corner.
AA
AF
AC
AD
AB
AE
W
L
M
G
J
C
D
H
N
R
U
A
B
E
F
K
P
T
V
Y
RAM_PA
RAM_PA
DDR[12]
DDR[17]
GPIO[12
RAM_D
RAM_D
ATA[10]
RAM_D
ATA[15]
RAM_D
ATA[21]
RAM_D
ATA[25]
RAM_D
ATA[29]
RITY[1]
RITY[7]
RAM_A
RAM_A
RAM_A
RAM_A
RAM_B
RAM_B
GPIO[1] GPIO[7] GPIO[8] GPIO[15
GPIO[5] GPIO[11
RAM_D
ATA[34]
RAM_D
ATA[35]
DDR[5]
DDR[9]
ATA[3]
GND
GND
W_E
W_H
GND
N/C
N/C
N/C
N/C
]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
RAM_PA
RAM_PA
DDR[10]
DDR[14]
DDR[18]
GPIO[13
RAM_D
RAM_D
RAM_D
ATA[13]
RAM_D
ATA[18]
RAM_D
ATA[24]
RAM_D
ATA[28]
RAM_A
RAM_A
RAM_A
RAM_A
RAM_A
RAM_B
RAM_B
RAM_B
GPIO[4] GPIO[6] GPIO[10
RAM_D
ATA[36]
RAM_D
ATA[40]
RAM_D
ATA[50]
RITY[0]
RITY[6]
DDR[4]
DDR[6]
ATA[1]
ATA[9]
W_A
W_D
W_G
N/C
N/C
N/C
]
]
RAM_PA
DDR[11]
DDR[15] RAM_A
GPIO[0] GPIO[3] GPIO[9] RAM_D
GPIO[14
RAM_D
RAM_D
ATA[12]
RAM_D
ATA[16]
RAM_D
ATA[23]
RAM_D
ATA[27]
RAM_D
ATA[31]
RITY[5]
RAM_A
DDR[2]
RAM_A
DDR[7]
RAM_A
RAM_A
RAM_B
RAM_B
RAM_B
RAM_D
ATA[37]
RAM_D
ATA[41]
RAM_D
ATA[48]
RAM_D
ATA[55]
ATA[5]
W_C
W_B
W_F
N/C
N/C
N/C
N/C
]
RAM_PA
DDR[13]
DDR[19]
IC_GND
RAM_D
RAM_D
RAM_D
RAM_D
ATA[14]
RAM_D
ATA[19]
RAM_D
ATA[26]
RAM_D
ATA[30]
RAM_A
RAM_A
RAM_A
RAM_R
RAM_D
ATA[38]
RAM_D
ATA[42]
RAM_D
ATA[47]
RAM_D
ATA[54]
RAM_D
ATA[56]
RITY[4]
DDR[3]
DDR[8]
SYSTE
M_RST
ATA[0]
ATA[4]
ATA[6]
N/C
N/C
N/C
W
]
]
RAM_PA
DDR[16]
IC_GND
GPIO[2] VDD_C
RAM_D
RAM_D
RAM_D
ATA[11]
RAM_D
ATA[17]
RAM_D
ATA[22]
RITY[3]
RAM_A
DDR[0]
RAM_A
SYSTE
M_DEB
RAM_D
ATA[32]
RAM_D
ATA[39]
RAM_D
ATA[43]
RAM_D
ATA[46]
RAM_D
ATA[53]
RAM_D
ATA[57]
RAM_D
ATA[61]
ATA[2]
ATA[7]
GND
GND
GND
N/C
N/C
N/C
N/C
RAM_PA
TEST_M
RAM_D
VDD_C
RAM_D
ATA[20]
VDD_C
RITY[2]
RAM_A
VDD_C
A1VDD
M_CLK
ATA[33]
VDD_C
RAM_D
ATA[44]
RAM_D
ATA[49]
RAM_D
ATA[58]
RAM_D
ATA[62]
DDR[1]
SYSTE
ODE[2]
ATA[8]
GND
ORE
ORE
ORE
GND
ORE
ORE
GND
N/C
N/C
N/C
N/C
N/C
IC
RAM_D
RAM_D
RAM_D
RAM_D
JTAG_T
JTAG_T
VDD_C
ATA[45]
ATA[51]
ATA[59]
ATA[63]
ORE
RST
N/C
N/C
N/C
N/C
N/C
DI
Figure 5 - ZL50130 Package View and Ball Positions
TEST_M
IC_GND CPU_AD
IC_GND CPU_AD
RAM_D
ATA[52]
RAM_D
ATA[60]
JTAG_T
ODE[0]
N/C
N/C
N/C
N/C
N/C
N/C
CK
TEST_M
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
JTAG_T
IC_GND CPU_AD
VDD_C
ODE[1]
DR[3]
DR[5]
ORE
N/C
N/C
N/C
N/C
N/C
N/C
DO
CPU_AD
CPU_AD
CPU_AD
JTAG_T
DR[10]
GND CPU_AD
DR[4]
DR[7]
DR[8]
N/C
N/C
N/C
N/C
N/C
N/C
MS
CPU_AD
CPU_AD
CPU_AD
CPU_AD
CPU_AD
DR[13]
DR[15]
DR[11]
DR[2]
DR[6]
DR[9]
GND
GND
GND
GND
GND
GND
N/C
N/C
N/C
N/C
N/C
N/C
CPU_AD
CPU_AD
CPU_AD
CPU_AD
CPU_AD
CPU_AD
VDD_C
DR[12]
DR[14]
DR[16]
DR[17]
DR[18]
DR[19]
GND
GND
GND
GND
GND
GND
ORE
N/C
N/C
N/C
N/C
N/C
Zarlink Semiconductor Inc.
CPU_AD
CPU_AD
CPU_AD
CPU_AD
VDD_C
DR[23]
DR[22]
DR[21]
DR[20]
GND
GND
GND
GND
GND
GND
GND
ORE
GND CPU_CSCPU_SD
N/C
N/C
N/C
N/C
N/C
ZL50130
CPU_TACPU_DA
CPU_CL
CPU_W
VDD_C
CPU_O
GND
GND
GND
GND
GND
GND
ORE
N/C
N/C
N/C
N/C
N/C
N/C
K
E
E
CPU_DA
CPU_SD
CPU_TS
VDD_C
CPU_D
REQ0
TA[8]
TA[1]
ACK2
_ALE
ACK1
ORE
GND
GND
GND
GND
GND
GND
N/C
N/C
N/C
N/C
N/C
10
CPU_DA
CPU_DA
CPU_IR
IC_VDD
CPU_D
TA[15]
REQ1
GND
GND
GND
GND
GND
GND
TA[7]
EQ1
N/C
N/C
N/C
N/C
N/C
N/C
_IO
IC
CPU_DA
CPU_DA
CPU_DA
CPU_DA
CPU_IR
TA[23]
TA[12]
TA[10]
TA[3]
EQ0
N/C
N/C
N/C
N/C
N/C
N/C
IC
CPU_DA
CPU_DA
CPU_DA
CPU_DA
CPU_DA
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_C
TA[22]
TA[16]
ORE
TA[6]
TA[4]
TA[0]
N/C
N/C
N/C
N/C
N/C
N/C
M2_RXC
CPU_DA
CPU_DA
CPU_DA
CPU_DA
CPU_DA
TA[30]
TA[21]
TA[14]
TA[9]
TA[5]
N/C
N/C
N/C
N/C
N/C
N/C
LK
M2_RXD
M2_TXE
CPU_DA
CPU_DA
CPU_DA
CPU_DA
VDD_C
TA[27]
TA[20]
TA[13]
ORE
TA[2]
N/C
N/C
N/C
N/C
N/C
V
R
M3_RXD
M1_RXE
M1_TXD
M1_TXD
M0_TXD
M2_RXD
M2_TXD
CPU_DA
CPU_DA
CPU_DA
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
TA[24]
TA[18]
TA[11]
GND
ORE
ORE
ORE
ORE
ORE
GND M0_TXD
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
[2]
[0]
[2]
[1]
[1]
V
R
M3_RXD
M0_RXD
M0_RXC
CPU_DA
CPU_DA
CPU_DA
M1_TXC
M1_REF
M1_TXD
M1_TXD
M0_TXE
M0_TXD
M2_TXE
TA[29]
TA[25]
TA[17]
GND
GND M3_TXD
GND M1_TXE
N/C
N/C
N/C
N/C
N/C
N/C
N/C
CLK
N/C
N/C
[3]
LK
[3]
[1]
[2]
[1]
[0]
LK
R
N
M3_RXD
M1_CRSM3_TXD
M1_RXC
M1_TXE
M0_TXE
M0_TXD
M2_RXD
M2_TXD
CPU_DA
CPU_DA
M2_LIN
KUP_LE
M_MDC M3_CRSM3_TXC
M0_LIN
KUP_LE
TA[28]
TA[19]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
[2]
[3]
LK
[3]
[2]
[2]
R
N
N
M3_RXD
M1_RXD
M2_RXD
CPU_DA
KUP_LE
M3_TXE
M0_TXC
M0_REF
M2_ACT
M2_RXE
M2_TXD
M3_LIN
IVE_LE
TA[26]
GND
GND
CLK
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
[1]
[0]
[2]
LK
[0]
[0]
N
R
M3_RXD
M3_TXE
M3_TXD
M1_RXD
M1_COLM1_RXD
M0_CRS
M0_RXD
M0_COLM0_RXD
M1_ACT
M2_CRSM0_ACT
M2_RXD
M2_TXD
CPU_DA
IVE_LE
TA[31]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
LK
[0]
[1]
[3]
[3]
[3]
R
V
M_MDIO
M3_RXE
M3_COL
M3_RXC
M3_TXD
M1_RXD
M1_RXD
M0_RXE
M0_RXD
M0_RXD
M3_ACT
M2_TXC
M2_COL
KUP_LE
M1_LIN
IVE_LE
IVE_LE
GND
GND
GND
N/C
N/C
N/C
N/C
N/C
N/C
LK
LK
[2]
[1]
[0]
[3]
[1]
[0]
R
V
R
AA
AF
AB
AC
AD
AE
W
L
M
G
J
A
B
C
D
E
H
K
N
P
R
U
V
Y
F
T
Data Sheet