ZL50130PBGA ZARLINK [Zarlink Semiconductor Inc], ZL50130PBGA Datasheet - Page 31

• Manufacturer Part Number: ZL50130PBGA
• Description: Ethernet Pseudo-Wires across a PSN
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.2
All External Memory Interface signals are 5 V tolerant.
All External Memory Interface outputs are high impedance while System Reset is LOW.
If the External Memory Interface is unused, all input pins may be left unconnected.
Active low signals are designated by a # suffix, in accordance with the convention used in common memory data
sheets.
RAM_DATA[63:0]
RAM_PARITY[7:0]
External Memory Interface
Signal
Table 7 - External Memory Interface Package Ball Definition
I/O
OT
OT
IU/
IU/
[63]
[62]
[61]
[60]
[59]
[58]
[57]
[56]
[55]
[54]
[53]
[52]
[51]
[50]
[49]
[48]
[47]
[46]
[45]
[44]
[43]
[42]
[41]
[40]
[39]
[38]
[37]
[36]
[35
[34]
[33]
[32]
[7]
[6]
[5]
[4]
AD7
AE6
AF5
AB8
AC7
AD6
AE5
AF4
AF3
AE4
AD5
AA8
AB7
AF2
AC6
AE3
AD4
AC5
AA7
AB6
AB5
AC4
AD3
AE2
AA5
AB4
AC3
AD2
AE1
AD1
W6
Y5
L1
L2
L3
L4
Package Balls
Zarlink Semiconductor Inc.
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
ZL50130
31
K3
K4
J1
J2
J3
J4
H1
H2
H3
J5
G1
J6
H4
G2
H5
G3
F1
G4
F2
F3
G5
E1
E2
G6
F5
F4
E3
E4
D1
E5
D2
D4
L5
L6
K1
K2
Buffer memory data.
Synchronous to rising edge of
SYSTEM_CLK.
Buffer memory parity.
Synchronous to rising edge of
SYSTEM_CLK. Bit [7] is parity
for data byte [63:56], bit [0] is
parity for data byte [7:0].
Description
Data Sheet