ZL50130PBGA ZARLINK [Zarlink Semiconductor Inc], ZL50130PBGA Datasheet - Page 8

• Manufacturer Part Number: ZL50130PBGA
• Description: Ethernet Pseudo-Wires across a PSN
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.2
A diagram of the ZL50130 device is given in Figure 4, which shows the major data flows between functional
components.
2.2.1
The Ethernet switch device aggregates Ethernet frames received from each customer into a single Ethernet
connection. Packets are forwarded on this connection to the ZL50130, and received by its customer-facing MAC
interface. Valid packets are passed to the Packet Classifier to determine the destination.
The Protocol Engine handles the data-plane requirements of the main higher level protocols (layers 4 and 5) used
in typical applications of the ZL50130. These include the Ethernet pseudo-wire control word (basically a 16-bit
sequence number), L2TPv3 connection ID, L2TP version 2 and UDP. The Protocol Engine can add a header to the
datagram containing up to 24 bytes. This header is largely static information, and is programmed directly to the
CPU. The header may contain a number of dynamic fields, including a length field, checksum, sequence number
and a timestamp. The location, and in some cases, the length of these fields is also programmable, allowing the
various protocols to be placed at variable locations within the header.
Packets ready for transmission are queued to the switch fabric interface by the Packet Transmit block. Four classes
of service are provided, allowing some packet streams to be prioritized over others. On transmission, the Packet
Transmit block appends a programmable header, which has been set up in advance by the control processor.
Typically this contains the data-link and network layer headers (layers 2 and 3), such as Ethernet IP, or the MPLS
tunnel and the VC labels. Finally, packets are sent out to the packet switched network by the PSN-facing MAC.
Basic Operation
PSN-Bound Flow
Provider Edge
Interworking Function
Phy
Phy
Phy
Phy
Phy
Phy
Phy
Phy
aggregation and
e.g. MVTX2604
MVTX2804
Ethernet
adaptation
functions
Switch
Figure 4 - ZL50130 Data Flows
ZL50130 Ethernet Pseudo-Wire Device
MAC
Zarlink Semiconductor Inc.
ZL50130
Host Processor Interface
memory management /
on-chip packet memory
protocol
engine
- add layer 2/3 headers
with DMA support
8
receive/classifier
packet transmit
packet
manager
task
MAC
Phy
PSN bound flow
CE bound flow
Data Sheet
Network
Packet
Switch