AM79C987 AMD [Advanced Micro Devices], AM79C987 Datasheet
AM79C987
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AM79C987 Summary of contents
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... GENERAL DESCRIPTION The Am79C987 Hardware Implemented Management Information Base (HIMIB) device is a highly integrated chip that simplifies building fully managed multiport re- peaters. The device integrates all the necessary counters, attributes, actions, and notifications specified by the Layer Management for 10 Mbyte/s Baseband Repeaters (IEEE 802 ...
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... Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver Attributes Port Number Single-Chip Ethernet Controller (with Microsoft Plug n’ Play support (IMR+ ) Am79C987 AMD CRS Data STR 802.3 DAT Receive JAM MAC ACK COL Status SCLK IMR+ ...
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... LOGIC SYMBOL 17305B-2 Am79C987 V D7–0 CRS DD CS STR C/D SCLK RD SI Am79C987 WR SO RDY DAT INT JAM RST ACK CK COL 17305B-3 3 ...
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... See Product Selector Guide and Valid Combination Valid combinations list configurations planned to be sup- JC ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C987 Valid Combinations ...
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... WR Write Strobe Input, Active LOW When this pin is asserted and the CS is active, a write operation is initiated. RD Read Strobe Input, Active LOW When this pin is asserted and the CS is active, a read operation is initiated. Am79C987 5 ...
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... Interrupt is driven LOW when any of the unmasked (enabled) interrupts occur Power This pin supplies + the device. Connect the IMR+ device Ground These two pins are the 0 V reference for the device. Connect the IMR+ device. SS Am79C987 DD ...
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... HIMIB device can be interfaced with any Ethernet con- troller with a general purpose serial interface (GPSI). The HIMIB device will record various network events oc- curring at that node of the network, and assign these gathered statistics to the AUI port. All TP ports statistics are invalid in this mode. Am79C987 7 ...
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... D Port will be the least significant byte. Note that the P and R registers can be accessed in any sequence prior to accessing the D Port. If either register is not written prior to accessing the D Port then the previous value register will be used. Am79C987 AMD ...
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... When specifying the Register or Attribute to be ac- cessed, the following command byte is written to the C Port. C Port Write 1 1 MSB R = [R4R3R2R1R0 Note that to access the R register the three most signifi- LSB cant bits of this byte must be one. Am79C987 Bank Register . . 31 Port (or Bank) Bank 1 Pointer ...
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... Register bytes long and can be read as well as written to in the least to most significant byte order. Note that the contents of all attribute registers are main- tained during an external reset. At power up, the values of all 4- and 6-byte attributes are random. Am79C987 AMD ...
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... Readable Octets Frame Check Sequence Errors Alignment Errors Frames Too Long Short Events Runts Collisions Late Events Very Long Events Data Rate Mismatches Auto Partitions Source Address Changes Reserved Last Source Address Am79C987 Bytes Access 1 R R[4:0] Bytes Access ...
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... D Port causes the value of this regis- bit 0 ter to be copied to the internal holding register. The data is then read from the holding register, without affecting this attribute. This sequence is repeated when the last byte is read and the D Port is accessed. bit 40 LSB Am79C987 AMD bit 0 bit 24 LSB ...
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... D7 D6 MSB This is a write only register. This register is used for sending a Set command to the IMR+ device. When a byte is written to this register, the HIMIB chip will serial- ize and transfer this byte to the IMR+ Management port. Am79C987 Device ...
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... AUI port. Bits denoted as X are undefined. D Port Read A X MSB Note that if the loopback path is not opera- tional, this bit will be set again when the next packet is transmitted via the AUI port. Am79C987 AMD ...
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... MSB LSB AUI Port P[4: R[4: Port Read/Write A X MSB The AUI port only uses the most significant bit (A) and all other bits are reserved. Software should be designed to write 0s into unused bits. Am79C987 ...
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... When writing the LSA regis- ter, if the sequence is aborted prior to the sixth consecu- tive write cycle, the internally stored register value is not updated. The sequence (read or write) may be aborted and restarted by programming the C Port. Am79C987 AMD ...
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... Frames LSB that have both framing errors and FCS errors are counted by this attribute, but not by the “Frame Check Sequence Errors” attribute. This attribute is a 32-bit counter with a minimum rollover time of 80 hours. Am79C987 bit 0 bit 24 LSB bit 0 bit 24 ...
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... Long Events” read-only attribute that counts the number of times the transmitter is active in excess of the MAU Jabber Lockup Protection (MJLP) Timer (4 ms – 7.5 ms). This attribute is a 32-bit counter with a mini- mum rollover time of 198 days. Am79C987 AMD bit 0 bit 24 LSB ...
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... This will cause the Source Address Changes attribute to bit 24 increment. Furthermore, setting the respective TP/AUI Port Source Address Change Interrupt Enable bit (in the LSB Port Control Registers), can be used to generate a hard- ware interrupt to signal the software to automatically disable this port. bit 0 bit 24 LSB Am79C987 bit 0 bit 24 LSB 19 ...
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... DAT and JAM are required for most applications. For more information, refer to the AMD IEEE 802.3 Re- peater Technical Manual. DAT CS JAM HIMIB C/D CRS CRS STR STR SCLK SCLK X1 D7–0 ACK RD WR COL RST RDY INT CK Am79C987 AMD Expansion Bus IMR+ REQ 17306B-5 ...
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... Operating ranges define those limits between which the func- tionality of the device is guaranteed. Test Condition VSS = 0.0 V IOL = 4.0 mA IOH = –0.4 mA IOLOD = < VIN and VIN < VDD +0.5 V VSS = 0.0 V VSS = 0.0 V VIN = VSS VIN = VDD fCK = 20 MHz Am79C987 . . . . . . . . . . . . + VDD + 0.5 V VIN VSS –0.5 V Min Max Unit –0.5 0 ...
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... CK Rising Edge Note: 1. See IMR+ data sheet for reset Test Condition (Note 1) (Note 1) (Note 1) Test Condition Test Condition Test Condition Am79C987 AMD Min Max Unit 49.995 50.005 ...
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... Data Out Hold after RD High tDOHLD tDISET Data In Setup Time with Respect to WR Rising Edge Data in Hold after WR High tDIHLD Test Condition CL = 100 100 100 pF Am79C987 Min Max Unit 150 ...
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... All Outputs and I/O Pins except RDY, INT RDY, INT Normal and Three-State Outputs VCC R1 Device Pin CL 17305B-7 B. Open-Drain Outputs (RDY, INT) Test Output Loads Test Circuit A B Am79C987 AMD V THRESHOLD 17305B (pF) 100 400 100 ...
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... AMD SWITCHING TEST LOADS (continued VDD 500 Device Pin 500 17305B-8 C. For Data Out (D7–0) Hold Only Am79C987 25 ...
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... Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State tCK tCKL tCKF tRST Clock and Reset Timing tCAHLD tDJSET Expansion Port Timing Am79C987 AMD KS000010 2.0 tRSTH tRSTS 17305B-9 tCASET tDJHOLD 17305B-10 ...
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... AMD SWITCHING WAVEFORMS CK tSCKD SCLK tCRSTS CRS tSCKF tSCKD tSCKR tSID tSID tSOS tSOH Management Port Timing tCRSTH Port Activity Timing Am79C987 17305B-11 17305B-12 27 ...
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... Refer to AMD’s IEEE 802.3 Repeater Technical Manual (PID #17314A) for more detailed access timing tRDYD tRDYH tDOUT Read Data tDISET Write Data Bus Interface Timing Am79C987 AMD tCDH tREST tCSH tREST tDOHLD tDIHLD 17305B-13 ...
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... APPENDIX A IMR+/HIMIB Security Features The Am79C981 Integrated Multiport Repeater Plus (IMR+) and the Am79C987 Hardware Implemented Management Information Base (HIMIB) Ethernet re- peater chip-set is capable of providing physical network security features. AMD will only make these features available to customers who are under an IMR+/HIMIB security non disclosure agreement (NDA) ...
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Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, b IMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, ...