AM79C987 AMD [Advanced Micro Devices], AM79C987 Datasheet - Page 16

• Manufacturer Part Number: AM79C987
• Description: Hardware Implemented Management Information Base (HIMIB) Device
• Manufacturer: AMD [Advanced Micro Devices]

TP Link State Change Interrupt Enable
P[4:0] = 2, R[4:0] = 2
Setting any of the bits in this register causes the INT pin
to be driven when there is a change in the Link Test
State of the corresponding TP port. The corresponding
status bit in the TP Link Status Change register is set
to 1.
D Port Read/Write
AUI Loop Back Error Interrupt Enable
P[4:0] = 2, R[4:0] = 3
Setting the A bit to 1 in this register causes the INT pin to
be driven when the IMR+ chip senses a Loop Back Error
condition at the AUI port.
D Port Read/Write
Note that the HIMIB device will continue generating in-
terrupts every time a packet is transmitted by the AUI
port while this condition exists. This does not necessar-
ily indicate a problem as an unconnected AUI port will
always report Loop Back Error.
AUI SQE Test Error Interrupt Enable
P[4:0] = 2, R[4:0] = 5
Setting the A bit to 1 in this register causes the INT pin to
be driven when the IMR+ chip senses a SQE Test Error
condition at the AUI port (attached MAU has SQE Test
enabled).
Note that the HIMIB device will continue generating in-
terrupts every time a packet is transmitted by the AUI
port, while this condition exists and this interrupt is
enabled.
D Port Read/Write
TP and AUI Source Address Change Interrupt
Enable
These two registers are used to enable or mask inter-
rupts caused by a change in the Source Address of a
port. A TP port connected to another repeater or an AUI
connected to a mixing (multiple DTEs) segment will
have frequent source address changes.
16
MSB
MSB
MSB
T7
A
A
T6
X
X
T5
X
X
T4
X
X
T3
X
X
T2
X
X
T1
X
X
P R E L I M I N A R Y
T0
X
X
LSB
LSB
LSB
Am79C987
A TP port connected to a single end station will only de-
tect a change of address if the end station is physically
changed to a different MAC address. The Last Source
Address (LSA) register (in the Port Attribute Registers)
of a port known to be connected to a single station can
be programmed with the Node ID (48-bit MAC address)
of the DTE. If the LSA is not programmed after power up
it will be overwritten by the source address of the first
packet received, and generate an interrupt if enabled.
TP Ports
P[4:0] = 2, R[4:0] = 6
D Port Read/Write
AUI Port
P[4:0] = 2, R[4:0] = 7
D Port Read/Write
The AUI port only uses the most significant bit (A) and all
other bits are reserved. Software should be designed to
write 0s into unused bits.
Port Attribute Registers
The Port Attribute Registers are accessed in the same
fashion as the Repeater, Status or Control Registers by
writing the appropriate Port Number and Register Num-
ber into the C Port. TP port number zero is accessed by
writing 0001 0000, TP port number one by writing
00010001 and so on. The AUI port attributes are ac-
cessed by writing 00011111 to the C Port.
Except for the Last Source Address (LSA) register, all
other registers are 4 bytes and read only. The (LSA) reg-
ister is 6 bytes long and its contents can be written and
read.
Once the C Port is programmed with a valid Port (Bank)
and Register (Attribute) Number, the corresponding at-
tribute is transferred to a holding register upon reading
the first byte. Subsequent accesses to the D Port read
the value in a least significant to most significant byte or-
der. When reading, once the last byte is read, the attrib-
ute value is re-transferred to the holding register and the
sequence can be restarted. When writing the LSA regis-
ter, if the sequence is aborted prior to the sixth consecu-
tive write cycle, the internally stored register value is not
updated. The sequence (read or write) may be aborted
and restarted by programming the C Port.
MSB
MSB
T7
A
T6
X
T5
X
T4
X
T3
X
T2
X
T1
X
AMD
T0
X
LSB
LSB