AM79C987 AMD [Advanced Micro Devices], AM79C987 Datasheet - Page 15

• Manufacturer Part Number: AM79C987
• Description: Hardware Implemented Management Information Base (HIMIB) Device
• Manufacturer: AMD [Advanced Micro Devices]

AUI SQE Test Error
P[4:0] = 1, R[4:0] = 5
This register is not valid for the IMR device
(Am79C980). When the HIMIB device is interfaced with
the IMR+ chip (Am79C981), this bit is set to 1 if the AUI
port is connected to a MAU with SQE Test enabled. For
the error to be detected, the network needs to be active
and a packet transmitted from the AUI port. Bits denoted
as X are undefined.
D Port Read
Note that if the error persists, once read, this bit will be
set again when the next packet is transmitted via the AUI
port.
TP and AUI Port Source Address Change Status
A change in the source address of a valid received
frame from any port causes the appropriate bit to be set
in these registers. The source address assigned to any
port after power up is indeterminate, and the first packet
received from any port will cause the SA changed status
bit for that port to be set.
TP Ports
P[4:0] = 1, R[4:0] = 6
TP Ports Source Address Changed Status:
D Port Read
AUI Port
P[4:0] = 1, R[4:0] = 7
AUI Port Source Address Changed Status:
D Port Read
Note: The Last Source Address attribute is program-
mable and can be used to store the expected Node ID
for this port. If the appropriate interrupt is also enabled,
then a change in the source address can be used to alert
the network manager of an unauthorized access. This is
particularly useful for segments that are supposed to be
connected to a single station.
TP and AUI Port Source Address Match Status
When the source address of the received packet from
any port matches that programmed into the Source Ad-
MSB
MSB
MSB
T7
A
A
AMD
T6
X
X
T5
X
X
T4
X
X
T3
X
X
T2
X
X
T1
X
X
P R E L I M I N A R Y
T0
X
X
LSB
LSB
LSB
Am79C987
dress Match Register (in the Repeater Registers), then
the appropriate bit will be set in the following registers:
TP Ports
P[4:0] = 1, R[4:0] = 8
D Port Read
AUI Port
P[4:0] = 1, R[4:0] = 9
D Port Read
Note: This function is useful for mapping an individual
Node ID to a specific port on the repeater.
Port Control Registers
These registers are accessed by writing the bit pattern
0000 0010 to the C port, i.e., P[4:0] = 2. All are read/write
registers. A set (1) control bit enables an interrupt or
function for the corresponding port. All control registers
are cleared upon reset.
TP and AUI Partition Status Change Interrupt
Enable
These two registers are used to enable or mask inter-
rupts caused by a change in the port partitioning status.
All interrupts are disabled and all status bits are cleared
upon hardware reset. Note that disabling an active inter-
rupt source causes the INT output to be placed into an
inactive state.
TP Ports
P[4:0] = 2, R[4:0] = 0
D Port Read/Write
AUI Port
P[4:0] = 2, R[4:0] = 1
D Port Read/Write
The AUI port only uses the most significant bit (A) and all
other bits are reserved. Software should be designed to
write 0s into unused bits.
MSB
MSB
MSB
MSB
T7
T7
A
A
T6
T6
X
X
T5
T5
X
X
T4
T4
X
X
T3
T3
X
X
T2
T2
X
X
T1
T1
X
X
T0
T0
X
X
LSB
LSB
LSB
LSB
15