AM79C987 AMD [Advanced Micro Devices], AM79C987 Datasheet - Page 12

• Manufacturer Part Number: AM79C987
• Description: Hardware Implemented Management Information Base (HIMIB) Device
• Manufacturer: AMD [Advanced Micro Devices]

DETAILED REGISTER FUNCTIONS
Status Register
The HIMIB Status Register can be accessed at any time
by reading the C Port.
The 8-bit quantity read has the following format:
C Port Read
I
E Interface Error. This bit is set if the HIMIB device is
S Source Address Match. This bit is set if the interrupt
X Reserved. The values of reserved bits are
Repeater, Port Status, Port Control and
Port Attribute Register Access
The bit pattern which must be written to the C Port in or-
der to correctly set the value of the R register to access
each of the registers is described in this section.
Repeater Register Bank
These registers are accessed by writing the bit pattern
0000 0000 to the C Port, i.e., P[4:0] = 0. Content of all
attribute counters are indeterminate upon power up.
Source Address Match Register
P[4:0] = 0, R[4:0] = 10
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
12
MSB
I
Interrupt. This bit reflects the state of the INT output
pin. If this bit is set to 1, then this HIMIB device is driv-
ing the INT pin. Note that the INT pin is an open drain
output and multiple devices may share the same in-
terrupt signal.
unable to communicate with the IMR+ device. This
bit is reset upon reading this register.
is caused by a source address match of the incoming
data packet. This bit remains set until the TP and/or
AUI Source Address Match Status register(s) in the
Port Status registers are read.
indeterminate.
D Port Read/Write
bit 47
MSB
bit 7
E
S
X
X
X
X
P R E L I M I N A R Y
bit 40
bit 0
LSB
X
LSB
Am79C987
This is a read/write register. The 6 bytes are read or writ-
ten in Low byte to High byte order. The sequence is
(re)started once the C Port is programmed for access to
this register. This register may be used to track nodes
within a LAN by reporting the port that received a packet
with a specific Source Address (SA). The Source Ad-
dress field of an incoming packet is always compared
with the 48-bit quantity stored in this register. The initial
value of this register is indeterminate.
A match is indicated by the HIMIB device by setting the
corresponding bit in the TP or AUI Source Address
Match Status register for the receiving port. If the corre-
sponding Source Address Match Interrupt Enable bit is
enabled, then the INT output pin is driven LOW. The set
bit(s) in the TP/AUI Source Address Match Status Reg-
isters are cleared when these registers are read.
Note that once a write sequence is started, all 6 bytes
must be written in order to change the contents of this
register.
Total Octets
P[4:0] = 0, R[4:0] = 12
Byte 0
Byte 1
Byte 2
Byte 3
This is a 4-byte attribute, read only register, whose con-
tents are incremented while the repeater is repeating
packet data. This counter is a truncated divide by 8 of
the total number of bits transmitted by the repeater. The
counter is incremented for non-collision packets with
valid SFD (Start of Frame Delimiter). This attribute in-
crements by same amount for all HIMIB devices con-
nected to the same expansion bus in a repeater.
The 4 bytes in this attribute are sequentially accessed
by reading the D Port, least significant byte first. Note
that once the C Port is programmed for access to this at-
tribute, reading the D Port causes the value of this regis-
ter to be copied to the internal holding register. The data
is then read from the holding register, without affecting
this attribute. This sequence is repeated when the last
byte is read and the D Port is accessed.
D Port Read
bit 31
MSB
bit 7
AMD
bit 24
bit 0
LSB