9UMS9610CKLF IDT [Integrated Device Technology], 9UMS9610CKLF Datasheet - Page 2

• Manufacturer Part Number: 9UMS9610CKLF
• Description: PC MAIN CLOCK
• Manufacturer: IDT [Integrated Device Technology]

Pin Description
IDT
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9UMS9610
PC MAIN CLOCK
1
2
3
4
5
6
7
8
9
TM
/ICST
CPU_STOP#_3.3
CLKPWRGD#/PD_3.3
X2
X1
VDDREF_3.3
REF_3.3_2x
GNDREF
VDDCORE_1.5
FSC_L_1.5
TEST_MODE_1.5
TEST_SEL_1.5
SCLK_3.3
SDATA_3.3
VDDCORE_1.5
VDDIO_1.5
DOT96C_LPR
DOT96T_LPR
GNDDOT
GNDLCD
LCD100C_LPR
LCD100T_LPR
VDDIO_1.5
VDDCORE_1.5
*CR#0_1.5
M
PC MAIN CLOCK
PIN NAME
TYPE
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
PWR 1.5V power for the PLL core
PWR 1.5V power for the PLL core
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 1.5V power for the PLL core
GND Ground pin for the REF outputs.
GND Ground pin for DOT clock output
GND Ground pin for LCD clock output
OUT Crystal output, Nominally 14.318MHz
OUT 3.3V 14.318 MHz reference clock. Default 2 load drive strength
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
This active-low input stops all CPU clocks that are set to be stoppable.
This level sensitive strobe determines when latch inputs are valid and are
ready to be sampled. When high, this asynchronous input places the
device into the power down state.
Crystal input, Nominally 14.318MHz.
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. 1.5V Max input voltage.
TEST_MODE is a real time input to select between Hi-Z and REF/N divider
mode while in test mode. Refer to Test Clarification Table. Max input
voltage is 1.5V.
TEST_SEL: latched input to select TEST MODE. Max input voltage is 1.5V
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Complement clock of low power differential pair for 96.00MHz DOT clock.
No 50ohm resistor to GND needed. No Rs needed.
True clock of low power differential pair for 96.00MHz DOT clock. No
50ohm resistor to GND needed. No Rs needed.
Complement clock of low power differential pair for LCD100 SS clock. No
50ohm resistor to GND needed. No Rs needed.
True clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
1.5V Clock request for SRC0, 0 = enable, 1 = disable
1 = All outputs are tri-stated for test
0 = All outputs behave normally.
DESCRIPTION
2
Logic Level
N/A
3.3
3.3
1.5
3.3
3.3
1.5
1.5
1.5
1.5
3.3
3.3
1.5
1.5
0.8
0.8
0.8
0.8
1.5
1.5
1.5
(V)
0
0
0
Tolerance (V)
1336—06/01/09
Input Level
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
3.3
1.5
3.3
1.5
1.5
3.3
3.3
3.3
3.3
1.5
1.5
1.5
1.5
1.5