K4H510438A-TCA0 SAMSUNG [Samsung semiconductor], K4H510438A-TCA0 Datasheet - Page 28

• Manufacturer Part Number: K4H510438A-TCA0
• Description: 128Mb DDR SDRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

128Mb DDR SDRAM
3.3.10 DM masking
cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the
corresponding data.(DM to data-mask latency is zero).
DM must be issued at the rising or falling edge of data strobe.
6. When terminating a burst Read command, the BST command must be issued L
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s).
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read
cycles before the clock edge at which the output buffers are tristated, where L
for read operations. This is shown in previous page Figure with examples for CAS latency (CL) of 1.5, 2,
2.5, 3 and 3.5 (only selected CAS latencies are required by the DDR SDRAM standards, the others are
optional).
< Burst Length=8 >
Command
DQ s
DQS
DM
CK
CK
WRITE
0
t
DQSS
Din 0 Din 1 Din 2 Din 3
NOP
masked by DM=H
1
Figure 18. DM masking timing
NOP
2
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Din 4 Din 5 Din 6 Din7
NOP
3
NOP
4
REV. 1.0 November. 2. 2000
NOP
5
NOP
BST
BST
6
equals the CAS latency
(“BST Latency”) clock
NOP
7
NOP
8