K4H510438A-TCA0 SAMSUNG [Samsung semiconductor], K4H510438A-TCA0 Datasheet - Page 42
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K4H510438A-TCA0
Manufacturer Part Number
K4H510438A-TCA0
Description
128Mb DDR SDRAM
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.K4H510438A-TCA0.pdf
(53 pages)
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128Mb DDR SDRAM
< Detailed test conditions for DDR SDRAM IDD1 & IDD7 >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
4. Timing patterns
8Mx16
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
per clock cycle. lout = 0mA
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
*50% of data changing at every burst
*50% of data changing at every burst
IDD6
*50% of data changing at every burst
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
Symbol
IDD4W
IDD2Q
IDD2P
IDD3P
IDD3N
IDD4R
IDD2F
IDD0
IDD1
IDD5
IDD7
Low power
Normal
Table 12. 128Mb DDR SDRAM IDD SPEC Table
typical
K4H281638B-TCA2
140
210
150
195
300
90
21
40
30
25
45
2
1
(DDR266A)
worst
155
245
165
210
340
95
25
45
35
30
50
2
1
typical
K4H281638B-TCB0
140
210
150
195
300
90
21
40
30
25
45
2
1
- 42 -
(DDR266B)
worst
155
245
165
210
340
95
25
45
35
30
50
2
1
REV. 1.0 November. 2. 2000
typical
K4H281638B-TCA0
135
155
110
180
275
80
20
35
27
20
35
2
1
(DDR200)
worst
150
175
125
190
300
85
24
40
32
25
40
2
1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Optional
Notes
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