AM49PDL127AH61IS SPANSION [SPANSION], AM49PDL127AH61IS Datasheet - Page 17

• Manufacturer Part Number: AM49PDL127AH61IS
• Description: 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
• Manufacturer: SPANSION [SPANSION]

AC Characteristics section contains timing specifica-
tion tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput at the
factory.
If the system asserts V
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
V
mal operation. Note that V
WP#/ACC for operations other than accelerated pro-
gramming, or device damage may result. In addition,
the WP#/ACC pin should be raised to V
use. That is, the WP#/ACC pin should not be left float-
ing or unconnected; inconsistent behavior of the de-
vice may result.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Command Se-
quence sections for more information.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE#f1, CE#f2 (PDL129 only) and RESET# pins are all
held at V
voltage range than V
only), and RESET# are held at V
± 0.3 V, the device will be in the standby mode, but the
standby current will be greater. The device requires
standard access time (t
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CMOS standby current specification.
December 18, 2003
CC3
HH
from the WP#/ACC pin returns the device to nor-
in the DC Characteristics table represents the
IO
± 0.3 V. (Note that this is a more restricted
IH
HH
CE
.) If CE#f1, CE#f2 (PDL129
on this pin, the device auto-
HH
) for read access when the
must not be asserted on
A D V A N C E
IH
, but not within V
Am49PDL127AH/Am49PDL129AH
CC
when not in
CC
I N F O R M A T I O N
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
150 ns. The automatic sleep mode is independent of
the CE#f1/CE#f2 (PDL129 only), WE#, and OE# con-
trol signals. Standard address access timings provide
new data when addresses are changed. While in
sleep mode, output data is latched and always avail-
able to the system. Note that during automatic sleep
mode, OE# must be at V
current to the stated sleep mode specification. I
the DC Characteristics table represents the automatic
sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to
reading array data. The operation that was interrupted
should be reinitiated once the device is ready to ac-
cept another command sequence, to ensure data in-
tegrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
held at V
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus monitor RY/BY# to deter mine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
Algorithms). The system can read data t
RESET# pin returns to V
Refer to the pSRAM AC Characteristics tables for RE-
SET# parameters and to Figure 15 for the timing dia-
gram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins (except for RY/BY#) are
placed in the highest Impedance state
READY
IL
but not within V
(during Embedded Algorithms). The
READY
IH
IH
.
IH
SS
before the device reduces
, output from the device is
±0.3 V, the standby cur-
(not during Embedded
SS
CC4
±0.3 V, the device
). If RESET# is
RH
after the
RP
CC5
ACC
, the
15
in
+