AM49PDL127AH61IS SPANSION [SPANSION], AM49PDL127AH61IS Datasheet - Page 78
AM49PDL127AH61IS
Manufacturer Part Number
AM49PDL127AH61IS
Description
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
Manufacturer
SPANSION [SPANSION]
Datasheet
1.AM49PDL127AH61IS.pdf
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PSEUDO SRAM AC CHARACTERISTICS
Notes:
1. CE1#s controlled.
2. t
3. t
4. t
5. A write occurs during the overlap (t
76
when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation.
A write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
write to the end of write.
CW
WR
AS
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
Address
CE1#s
CE2s
UB#s, LB#s
WE#
Data In
Data Out
Figure 29. Pseudo SRAM Write Cycle—CE1#s Control
A D V A N C E
WP
) of low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low
Am49PDL127AH/Am49PDL129AH
High-Z
t
AS
(See Note 2 )
I N F O R M A T I O N
(See Note 3)
WR
t
t
AW
applied in case a write ends as CE1#s or WE# going high.
CW
t
(See Note 5)
WC
t
BW
t
WP
t
DW
Data Valid
WP
t
WR
is measured from the beginning of
t
DH
(See Note 4)
High-Z
December 18, 2003
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