AM49PDL127AH61IS SPANSION [SPANSION], AM49PDL127AH61IS Datasheet - Page 79

• Manufacturer Part Number: AM49PDL127AH61IS
• Description: 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
• Manufacturer: SPANSION [SPANSION]

PSEUDO SRAM AC CHARACTERISTICS
Notes:
1. UB#s and LB#s controlled.
2. t
3. t
4. t
5. A write occurs during the overlap (t
December 18, 2003
when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation.
A write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
write to the end of write.
CW
WR
AS
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
CE1#s
CE2s
Address
UB#s, LB#s
WE#
Data In
Data Out
A D V A N C E
WP
Figure 30. Pseudo SRAM Write Cycle—
) of low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low
High-Z
Am49PDL127AH/Am49PDL129AH
(See Note 4)
t
AS
UB#s and LB#s Control
I N F O R M A T I O N
WR
(See Note 2)
t
CW
t
applied in case a write ends as CE1#s or WE# going high.
t
AW
WC
(See Note 5)
t
t
CW
(See Note 2)
BW
t
WP
t
DW
Data Valid
WP
t
WR
t
is measured from the beginning of
DH
(See Note 3)
High-Z
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