K9F1208B0C SAMSUNG [Samsung semiconductor], K9F1208B0C Datasheet - Page 9

• Manufacturer Part Number: K9F1208B0C
• Description: 64M x 8 Bits NAND Flash Memory
• Manufacturer: SAMSUNG [Samsung semiconductor]

K9F1208U0C
K9F1208R0C
Product Introduction
Table 1. Command Sets
NOTE : 1. The 00h/01h command defines starting address of the 1st/2nd half of registers.
The K9F1208X0C is a 528Mbits(553,648,218 bits) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col-
umns are located from column address of 512 to 527. A 528-bytes data register is connected to memory cell arrays accommodating
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
32 pages formed two NAND structures. A NAND structure consists of 16 cells. Total 135,168 NAND structures reside in a block. The
program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory
array consists of 4,096 separately erasable 16K-bytes blocks. It indicates that the bit by bit erase operation is prohibited on the
K9F1208X0C.
The K9F1208X0C has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 64M byte physical space requires
26 addresses, thereby requiring four cycles for byte-level addressing : 1 cycle of column address, 3 cycles of row address, in that
order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-
ation, however, only the 3 cycles of row address are used. Device operations are selected by writing specific commands into the
command register. Table 1 defines the specific commands of the K9F1208X0C.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
Read 1
Read 2
Read ID
Reset
Page Program
Block Erase
Block Protect 1
Block Protect 2
Block Protect 3
Read Status
Read Protection Status
After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h)
on the next cycle.
Function
K9F1208B0C
1’st Cycle
00h/01h
50h
90h
FFh
80h
60h
41h
42h
43h
70h
7Ah
(1)
9
2’nd Cycle
D0h
10h
-
-
-
-
-
-
-
-
-
FLASH MEMORY
Acceptable Command
during Busy
O
O