K9F1208D0A SAMSUNG [Samsung semiconductor], K9F1208D0A Datasheet
K9F1208D0A
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K9F1208D0A Summary of contents
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Document Title 64M x 8 Bit , 32M x 16 Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 0.1 TBGA(K9F12XXX0A-DCB0/DIB0) size information is changed. (before /0.8mm pitch , Width 1.0 mm (after ) To Be Decided. 0.2 TBGA(K9F12XXX0A-DCB0/DIB0) size information is changed. (before /0.8mm pitch , Width 1.0 mm, to (after) 8 ...
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... Before 45 15 After 60 20 1.2 1. K9F1208Q0A-DC(I)B0,K9F1216Q0A-DC(I)B0, K9F1208D0A-DC(I)B0, K9F1216D0A-DC(I)B0,K9F1208U0A-DC(I)B0, K9F1216U0A-DC(I)B0 are deleted. 1.3 1. Add the Protrusion/Burr value in WSOP1 PKG Diagram. 1.4 1. PKG(TSOP1, WSOP1) Dimension Change Note : For more detailed features and specifications including FAQ, please refer to Samsung’ s Flash web site. ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A 64M x 8 Bit / 32M x 16 Bit NAND Flash Memory PRODUCT LIST Part Number K9F1208D0A-Y,P K9F1216D0A-Y,P K9F1208U0A-Y,P K9F1208U0A-V,F K9F1216U0A-Y,P FEATURES Voltage Supply - 2.65V device(K9F12XXD0A) : 2.4~2.9V - 3.3V device(K9F12XXU0A) : 2.7 ~ 3.6 V Organization - Memory Cell Array - X8 device(K9F1208X0A) : (64M + 2048K)bit x 8 bit - X16 device(K9F1216X0A) : (32M + 1024K)bit x 16bit ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A PIN CONFIGURATION (TSOP1) X16 X8 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C R/B R N.C N.C N.C N.C Vcc Vcc Vss Vss N.C N.C N.C N.C CLE CLE ALE ALE N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 0~8 0.45~0.75 0.018~0.030 K9F12XXU0A-YCB0,PCB0/YIB0,PIB0 ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A PIN CONFIGURATION (WSOP1) N.C N.C DNU N.C N.C N.C R DNU N.C Vcc Vss N.C DNU CLE ALE WE WP N.C N.C DNU N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F #1 #24 K9F1208U0A-VCB0,FCB0/VIB0,FIB0 ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The 0 7 (K9F1208X0A) I/O pins float to high-z when the chip is deselected or when the outputs are disabled. I/O ~ I/O I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper- ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Figure 1-1. K9F1208X0A (X8) FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-1. K9F1208X0A (X8) ARRAY ORGANIZATION 128K Pages 1st half Page Register ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Figure 1-2. K9F1216X0A (X16) FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-2. K9F1216X0A (X16) ARRAY ORGANIZATION 128K Pages ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Product Introduction The K9F1208X0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte(x8 device), 264word(x16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Memory Map The device is arranged in four 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte(X8 device) or 264 word(X16 device) page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F12XXX0A-XCB0 Temperature Under Bias K9F12XXX0A-XIB0 K9F12XXX0A-XCB0 Storage Temperature K9F12XXX0A-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A DC AND OPERATING CHARACTERISTICS Parameter Symbol tRC=50ns, CE=V Sequential Read Operating I OUT Current Program Erase Stand-by Current(TTL CE=V SB Stand-by Current(CMOS CE=V SB Input Leakage Current Output Leakage Current I/O pins Input High Voltage V IH* Except I/O pins ...
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... Read Mode Write Mode Data Input X Data Output H X During Read(Busy) on K9F1208U0A-Y,P,V,F or K9F1208D0A-Y,P During Read(Busy) on the devices except K9F1208U0A-Y,P,V K9F1208D0A-Y During Program(Busy During Erase(Busy Write Protect X 0V/V (2) Stand- FLASH MEMORY Typ ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A PROGRAM / ERASE CHARACTERISTICS Parameter Program Time Dummy Busy Time for Multi Plane Program Number of Partial Program Cycles in the Same Page Block Erase Time AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT Parameter Symbol K9F12XXD0A CLE setup Time t CLS ...
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... K9F1208U0A- Last RE High to Busy(at sequential read) Y,P,V High to Ready(in case of interception read) K9F1208D0A- CE High Hold Time(at the last serial read) Y,P only NOTE reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us break the sequential read cycle, CE must be held high for longer time than tCEH. ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A NAND Flash Technical Notes Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Pointer Operation of K9F1208X0A(X8) Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’ 00h’ command sets the pointer to ’ A’ area(0~255byte), ’ 01h’ command sets the pointer to ’ B’ area(256~511byte), and ’ 50h’ command sets the pointer to ’ ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Pointer Operation of K9F1216X0A(X16) Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’ 00h’ command sets the pointer to ’ A’ area(0~255word), and ’ 50h’ command sets the pointer to ’ B’ area(256~263word). With these commands, the starting column address can be set to any of a whole page(0~263word). ’ ...
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... Figure 8. Read Operation with CE don’ t-care. CLE CE RE ALE R/B WE I/O X 00h Start Add.(4Cycle) Data Input I K9F1208U0A-Y,P,V,F or K9F1208D0A-Y,P CE must be held low during FLASH MEMORY CE don’ t-care Data Input t CEA t REA out CE don’ t-care Data Output(sequential) 10h ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Device K9F1208X0A(X8 device) K9F1216X0A(X16 device) NOTE: 1. I/O8~15 must be set to "0" during command or address input. I/O8~15 are used only for data bus. Command Latch Cycle CLE CE WE ALE I/O X Address Latch Cycle t CLS CLE ALS ALE I/O X I/O I/ ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Input Data Latch Cycle CLE CE t ALS ALE I/Ox Serial access Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 0 DIN 1 (CLE=L, WE=H, ALE=L) ...
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... X8 device : m = 528 , Read CMD = 00h or 01h X16 device : m = 264 , Read CMD = 00h t CLR t CLS t CLH WHR 70h On K9F1208U0A-Y,P,V,F or K9F1208D0A-Y,P CE must be held low during Dout Page(Row) Address Busy NOTES : 1) is only valid on ...
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... Valid Address Don care FLASH MEMORY On K9F1208U0A-Y,P,V,F or K9F1208D0A-Y,P CE must be held low during tR t CHZ Dout N+2 Dout N Dout N+1 On K9F1208U0A-Y,P,V,F or K9F1208D0A-Y,P CE must be held low during Dout n+M Selected Row 512 n+m 16 Start address M ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Sequential Row Read Operation CLE CE WE ALE RE 00h I R/B M Page Program Operation CLE ALE RE 80h I Sequential Data Column Input Command Address R/B (Within a Block) Dout Ready ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A BLOCK ERASE OPERATION CLE ALE RE I/O 60h Page(Row) Address R/B Auto Block Erase Setup Command (ERASE ONE BLOCK DOh Erase Command 27 FLASH MEMORY t BERS 70h I/O 0 Busy I/O =0 Successful Erase 0 Read Status I/O =1 Error in Erase ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A FLASH MEMORY 28 ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Multi-Plane Block Erase Operation CLE ALE RE I/O 60h Page(Row) Address R/B Block Erase Setup Command Max. 4 times repeatable * For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command. Ex.) Four-Plane Block Erase Operation ...
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... Byte Device Code Must be don’ t -cared 3 rd Byte th Supports Multi Plane Operation 4 Byte t REA 00h ECh Address. 1cycle Maker Code 30 FLASH MEMORY Device C0h A5h Code Multi Plane Code Device Device Code K9F1208D0A 76h K9F1208U0A 76h K9F1216D0A XX56h K9F1216U0A XX56h ...
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... Copy-Back Program Operation CLE ALE RE 00h I Column Page(Row) Address Address R/B On K9F1208U0A-Y,P,V,F or K9F1208D0A-Y,P CE must be held low during 8Ah Column Address Busy Copy-Back Data Input Command 31 FLASH MEMORY t t PROG WB 10h ...
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... CE high. When the page address moves onto the next block, read command and address must be given. Figures 9, 10 show typical sequence and timings for sequential row read operation. ). The system controller can detect the completion are ignored. The Read1 command(00h/01h) is needed K9F1208U0A-Y,P,V,F or K9F1208D0A-Y,P 32 FLASH MEMORY : 0 ...
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... X8 device : X16 device : NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. 01h command is only available on X8 device(K9F1208X0A). On K9F1208U0A-Y,P,V,F or K9F1208D0A-Y,P CE must be held low during & & ...
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... The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read- out, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the next block, read command and address must be given. On K9F1208U0A-Y,P,V,F or K9F1208D0A-Y,P CE must be held low during & ...
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... Read Status command mode until another valid command is written to the command register. Figure 11. Program & Read Status Operation R/B I 80h Address & Data Input & 528 Byte Data (only for K9F1208U0A-Y,P,V,F or K9F1208D0A-Y Data Output 1st 25 Data Field Spare Field t PROG 10h ~ ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A BLOCK ERASE The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Restriction in addressing with Multi Plane Page Program While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for the selected pages at one operation must be the same. Figure 14 shows an example where 2nd page of each addressed block is selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure15. Figure 14. Multi-Plane Program & ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Copy-Back Program The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Multi-Plane Copy-Back Program Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is equipped with four memory planes, activating the four sets of 528 bytes(x8 device) or 264words(x16 device)page registers enables a simultaneous Multi-Plane Copy-Back programming of four pages. Partial activation of four planes is also permitted. ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A FLASH MEMORY 40 ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired ...
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... Read ID mode until further commands are issued to it. Figure 21 shows the operation sequence. Figure 21. Read ID Operation 1 CLE CE WE ALE RE I 90h Address. 1cycle t CEA WHR t REA ECh 00h Maker code Device K9F1208D0A K9F1208U0A K9F1216D0A K9F1216U0A 42 FLASH MEMORY Device A5h Code Device code Multi-Plane code Device Code 76h 76h XX56h XX56h C0h ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A 300n 200n 100n 300n 200n 100n Rp value guidance Rp(min, 2.65V part) = Rp(min, 3.3V part) = where I is the sum of the input currents of all devices tied to the R/B pin. L Rp(max) is determined by maximum permissible limit Vcc = 2.65V 2.3 Ibusy 1 ...
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... K9F1208D0A K9F1216D0A K9F1208U0A K9F1216U0A Data Protection & Power-up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.8V(2.65V device), 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down ...