K9F1208D0A SAMSUNG [Samsung semiconductor], K9F1208D0A Datasheet - Page 8

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K9F1208D0A

Manufacturer Part Number
K9F1208D0A
Description
64M x 8 Bit , 32M x 16 Bit NAND Flash Memory
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
K9F1208D0A
K9F1208U0A
Figure 1-2. K9F1216X0A (X16) FUNCTIONAL BLOCK DIAGRAM
Figure 2-2. K9F1216X0A (X16) ARRAY ORGANIZATION
NOTE : Column Address : Starting Address of the Register.
V
V
(=4,096 Blocks)
2nd Cycle
3rd Cycle
4th Cycle
CC
1st Cycle
SS
128K Pages
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
CE
RE
WE
Command
A
A
I/O 0
A
A
9
A
A
0
17
25
- A
0
9
- A
K9F1216D0A
K9F1216U0A
25
7
I/O 1
A
A
A
L*
10
18
1
(=256 Words)
Page Register
& High Voltage
CLE ALE
Page Register
Control Logic
256Word
256 Word
Command
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Generator
Register
I/O 2
A
A
A
L*
11
19
2
WP
I/O 3
A
A
A
L*
12
20
3
8 Word
8 Word
I/O 4
A
A
A
L*
13
21
4
8
I/O 5
A
A
A
L*
I/O 0 ~ I/O 15
14
22
5
Global Buffers
(256 + 8)Word x 131072
Page Register & S/A
I/O Buffers & Latches
5126M + 16M Bit
I/O 6
A
A
A
L*
NAND Flash
15
23
16 bit
6
Y-Gating
ARRAY
1 Block =32 Pages
= (8K + 256) Word
1 Page = 264 Word
1 Block = 264 Word x 32 Pages
1 Device = 264Words x 32Pages x 4096 Blocks
I/O 7
A
A
A
L*
16
24
7
= (8K + 256) Word
= 528 Mbits
I/O8 to 15
L*
L*
L*
L*
Output
Driver
FLASH MEMORY
Column Address
Row Address
(Page Address)
V
V
CC/
SS
I/0 0
I/0 15
V
CCQ

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