HYS64T256020HU-3-A QIMONDA [Qimonda AG], HYS64T256020HU-3-A Datasheet

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560 20 H U– ]– 560 20 H U– ]– ...

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... HYS64T256020HU–[3/3S]–A, HYS72T256020HU–[3/3S]–A, HYS64T256020HU–[3.7/5]–A, HYS72T256020HU–[3.7/5]–A Revision History: 2006-09, Rev. 1.32 Page Subjects (major changes since last revision) All Qimonda update All Adapted internet edition Previous Revision: 2006-06, Rev. 1. Ordering Information Table: Corrected “Compliance Code”, “PC2–5300” for –3S; corrected “Footnote”. ...

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... Overview This chapter gives an overview of the 240-Pin Unbuffered DDR2 SDRAM Modules product family and describes its main characteristics. 1.1 Features • 240-Pin PC2–5300, PC2–4200 and PC2–DDR2 SDRAM memory modules • 256M × 64 non-ECC and 256M × 72 ECC module organization, and 128M × 8 chip organization • ...

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... CK3 t 15 RCD RAS Internet Data Sheet HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules TABLE 2 Performance table for –3.7 Unit — MHz MHz MHz TABLE 3 Performance table for –5 Unit — MHz ...

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... PC2–3200U–333–11–B1 1) All part numbers end with a place code, designating the silicon die revision. Example: HYS64T256020HU–3.7–A, indicating Rev. “A” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see 2) The Compliance Code is printed on the module label and describes the speed grade, for example “ ...

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... GByte 2 256M ×72 2 GByte 2 1) Product Type DRAM Components HYS64T256020HU HYB18T1G800AF HYS72T256020HU HYB18T1G800AF 1) Green Product 2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet. Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules ...

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... Pin Configurations 2.1 Pin Configuration The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in in columns Pin and Buffer Type are explained in for non-ECC modules (×64) and Figure 2 Ball No. Name Pin Buffer Type Type Clock Signals 185 CK0 I SSTL 137 CK1 ...

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... Note: 1 Gbit based module and 512M Not Connected × Note: Module based on 1 Gbit 16 × Module based on 512 Mbit 16 or smaller Address Signal 14 Note: Modules based on 2 Gbit Not Connected Note: Modules based on 1 Gbit or smaller Data Bus 63:0 8 Internet Data Sheet × ...

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... DQ39 I/O SSTL 89 DQ40 I/O SSTL 90 DQ41 I/O SSTL 95 DQ42 I/O SSTL 96 DQ43 I/O SSTL 208 DQ44 I/O SSTL 209 DQ45 I/O SSTL 214 DQ46 I/O SSTL 215 DQ47 I/O SSTL Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Function Data Bus 63:0 9 Internet Data Sheet ...

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... NC — 168 CB7 I/O SSTL NC NC — Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Function Data Bus 63:0 Check Bit 0 Not Connected Check Bit 1 Not Connected Check Bit 2 Not Connected Check Bit 3 Not Connected Check Bit 4 Not Connected ...

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... REF V 238 PWR — DDSPD Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Function Data Strobe Bus 8:0 Complement Data Strobe Bus 8:0 Data Mask Bus 8:0 Serial Bus Clock Serial Bus Data Serial Address Select Bus 2:0 I/O Reference Voltage EEPROM Power Supply ...

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... Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Function I/O Driver Power Supply Power Supply Ground Plane On-Die Termination Control 0 On-Die Termination Control 1 Note: 2 Rank modules Not Connected Note: 1 Rank modules Not connected 12 Internet Data Sheet ...

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... Open Drain. The corresponding pin has 2 operational states, active low and tri-state, and allows multiple devices to share as a wire-OR. Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Abbreviations for Pin Type Abbreviations for Buffer Type 13 Internet Data Sheet ...

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... Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Pin Configuration UDIMM ×64 (240 Pin) 14 Internet Data Sheet FIGURE 1 ...

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... Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Pin Configuration UDIMM ×72 (240 Pin) 15 Internet Data Sheet FIGURE 2 ...

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... When operating this product in the 85 ° °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Rating Min. V –1.0 ...

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... DDQ V 2) Peak to peak AC noise on may not exceed ± 2% REF 3) Input voltage for any connector pin under test ≤ Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Symbol Values Min. Max +65 OPR T ...

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... — RCD t 12 — stabilizes. During the period before REF REF Internet Data Sheet HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules TABLE 14 DDR2–667D Unit Note –3S t 5–5–5 CK Min. Max. — 1)2)3) 1)2)3)4) 3. ...

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... RAS RCD stabilizes. During the period before REF REF Internet Data Sheet HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules TABLE 15 Unit Note t CK Max. — 1)2)3) 1)2)3) 1)2)3) 1)2)3)4)5) 70000 ns 1)2)3)4) — ns 1)2)3)4) — ns 1)2)3)4) — ...

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... RAS RCD stabilizes. During the period before REF REF Internet Data Sheet HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules TABLE 16 Unit Note t CK Max. — 1)2)3) 1)2)3) 1)2)3) 1)2)3)4)5) 70000 ns 1)2)3)4) — ns 1)2)3)4) — ns 1)2)3)4) — ...

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... Address and control input setup time Address and control input hold time Read preamble Read postamble Active to precharge command Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Timing Parameter by Speed Grade - DDR2–667 Symbol DDR2–667 Min. Max. t –450 ...

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... The input reference level (for timing reference CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Symbol DDR2–667 Min. Max. ...

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... V level for a rising signal and IL.DC shows a method to calculate these points when the device is no longer driving ( 23 Internet Data Sheet HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules V stabilizes, CKE = 0 recognized as low. DDQ t ‘ represents the actual of the input clock CK ...

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... VOH - 2x mV VTT + x mV VOL + 2x mV VTT - x mV VOL + x mV VTT - 2*T1-T2 tLZ,tRPRE end point begin point 24 Internet Data Sheet HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules t of the input clock. (output JIT.PER t = – JIT.PER.MIN RPRE.MAX(DERATED) RPRE.MAX t of the input clock ...

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... DQS CK CK Rev. 1.32, 2006-09 03062006-5RK8-1X8J Differential input waveform timing - tDH tDS tDH tDS Differential input waveform timing - tIH tIH tIS tIS 25 Internet Data Sheet HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules FIGURE and DDQ V min IH(ac) V min IH(dc) V REF(dc) V ...

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... DQS low-impedance from Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Timing Parameter by Speed Grade - DDR2–533 Symbol DDR2–533 Min. Max. t – ...

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... XSRD 5)6)7)8) V stabilizes. During the period before REF REF refers to the application clock period. WR refers and ). Internet Data Sheet HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules 1)2)3)4)5) Unit Note 6)7) Max. 400 ps µs 14)15) 7.8 µs 16)18) 3.9 17) — ns — ns — 14) 1 ...

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... For each of the terms, if not already an integer, round to the next highest integer can be used. In “low active power-down mode” (MR, A12 =”1”) a slow XARD 28 Internet Data Sheet HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Table 4 “Ordering Information for RoHS [cycles] = (ns)/ (ns) rounded MIN ...

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... DQS low-impedance from Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Timing Parameter by Speed Grade - DDR2-400 Symbol DDR2–400 Min. Max. t – ...

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... XSRD 5)6)7)8) V stabilizes. During the period before REF REF refers to the application clock period. WR refers and ). Internet Data Sheet HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules 1)2)3)4)5) Unit Note 6)7) Max. 450 ps µs 14)15) 7.8 µs 16)18) 3.9 17) — ns — ns — 14) 1 ...

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... For each of the terms, if not already an integer, round to the next highest integer can be used. In “low active power-down mode” (MR, A12 =”1”) a slow XARD 31 Internet Data Sheet HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Table 4 “Ordering Information for RoHS [cycles] = (ns)/ (ns) rounded MIN ...

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... ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. t Both are measured from . AOFD Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules ODT AC Characteristics and Operating Conditions for DDR2-667 Values Min. Max ...

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... CKE is HIGH HIGH between valid RFC RFC.MIN t = interval, CKE is LOW and CS is HIGH between valid RFC REFI 33 Internet Data Sheet HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules TABLE 22 I Measurement Conditions DD Symbol Note 1)2)3)4)5) I DD0 6) I DD1 t t ...

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... Definitions for see Table For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode 5) For details and notes see the relevant Qimonda component data sheet ...

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... Product Type HYS64T256020HU–3–A Organization 2 GB ×64 2 Ranks –3 I 728 DD0 I 888 DD1 I 960 DD2N I 96 DD2P I 640 DD2Q I 1040 DD3N I 336 DD3P_0 (fast) I 112 DD3P_1 (slow) I 1448 DD4R I 1448 DD4W I 1648 DD5B I 112 DD5D I 96 DD6 I 2088 DD7 1) Calculated values from component data. ODT disabled. ...

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... Product Type HYS64T256020HU–3S–A Organization 2 GB ×64 2 Ranks –3S I 696 DD0 I 848 DD1 I 960 DD2N I 96 DD2P I 624 DD2Q I 1040 DD3N I 336 DD3P_0 (fast) I 112 DD3P_1 (slow) I 1448 DD4R I 1448 DD4W I 1648 DD5B I 112 DD5D I 96 DD6 I 1984 DD7 1) Calculated values from component data. ODT disabled. ...

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... Product Type HYS64T256020HU–3.7–A Organization 2 GB ×64 2 Ranks –3.7 I 646 DD0 I 726 DD1 I 736 DD2N I 91 DD2P I 512 DD2Q I 800 DD3N I 272 DD3P_0 (fast DD3P_1 (slow) I 1206 DD4R I 1166 DD4W I 1526 DD5B I 112 DD5D I 91 DD6 I 1886 DD7 1) Calculated values from component data. ODT disabled. ...

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... Product Type HYS64T256020HU–5–A Organization 2 GB ×64 2 Ranks –5 I 606 DD0 I 686 DD1 I 560 DD2N I 91 DD2P I 448 DD2Q I 640 DD3N I 208 DD3P_0 (fast DD3P_1 (slow) I 966 DD4R I 926 DD4W I 1486 DD5B I 112 DD5D I 92 DD6 I 1686 DD7 1) Calculated values from component data. ODT disabled. ...

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... Table 28 “SPD codes for HYS64T256020HU–3–A” on Page 39 • Table 29 “SPD codes for HYS64T256020HU–3S–A” on Page 43 • Table 30 “SPD codes for HYS64T256020HU–3.7–A” on Page 47 • Table 31 “SPD codes for HYS64T256020HU–5–A” on Page 51 Product Type Organization Label Code JEDEC SPD Revision Byte# ...

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... Delta CASE.MAX 4R4W 48 Psi(T-A) DRAM ∆ (DT0) 0 ∆ T (DT2N, UDIMM) or ∆ ∆ (DT2P) 2P Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS64T256020HU–3–A 2 GByte ×64 2 Ranks (×8) PC2–5300U–444 Rev. 1.1 HEX ...

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... Product Type, Char 10 83 Product Type, Char 11 84 Product Type, Char 12 Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules HYS64T256020HU–3–A HYS72T256020HU–3–A 2 GByte 2 GByte ×64 ×72 2 Ranks (×8) 2 Ranks (×8) PC2–5300U–444 PC2–5300E–444 Rev ...

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... Module Serial Number 99 - 127 Not used 128 - Blank for customer use 255 Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules HYS64T256020HU–3–A HYS72T256020HU–3–A 2 GByte 2 GByte ×64 ×72 2 Ranks (×8) 2 Ranks (×8) PC2–5300U–444 PC2– ...

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... RRD.MIN t 29 [ns] RCD.MIN Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules SPD codes for HYS64T256020HU–3S–A HYS64T256020HU–3S–A HYS72T256020HU–3S–A 2 GByte 2 GByte ×64 ×72 2 Ranks (×8) 2 Ranks (×8) PC2–5300U–555 PC2–5300E–555 Rev ...

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... T 57 (DT7 Psi(ca) PLL 59 Psi(ca) REG ∆ (DTPLL) PLL ∆ (DTREG) / Toggle Rate REG 62 SPD Revision Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS64T256020HU–3S–A 2 GByte ×64 2 Ranks (×8) PC2–5300U–555 Rev. 1.2 HEX ...

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... Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules HYS64T256020HU–3S–A HYS72T256020HU–3S–A 2 GByte 2 GByte ×64 ×72 2 Ranks (×8) 2 Ranks (×8) PC2–5300U–555 PC2– ...

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... Description 99 - 127 Not used 128 - Blank for customer use 255 Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules HYS64T256020HU–3S–A HYS72T256020HU–3S–A 2 GByte 2 GByte ×64 ×72 2 Ranks (×8) 2 Ranks (×8) PC2–5300U–555 PC2–5300E–555 Rev ...

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... RRD.MIN t 29 [ns] RCD.MIN Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules SPD codes for HYS64T256020HU–3.7–A HYS64T256020HU–3.7–A HYS72T256020HU–3.7–A 2 GByte 2 GByte ×64 ×72 2 Ranks (×8) 2 Ranks (×8) PC2–4200U–444 PC2–4200E–444 Rev ...

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... T 57 (DT7 Psi(ca) PLL 59 Psi(ca) REG ∆ (DTPLL) PLL ∆ (DTREG) / Toggle Rate REG 62 SPD Revision Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS64T256020HU–3.7–A 2 GByte ×64 2 Ranks (×8) PC2–4200U–444 Rev. 1.1 HEX ...

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... Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules HYS64T256020HU–3.7–A HYS72T256020HU–3.7–A 2 GByte 2 GByte ×64 ×72 2 Ranks (×8) 2 Ranks (×8) PC2–4200U–444 PC2– ...

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... Description 99 - 127 Not used 128 - Blank for customer use 255 Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules HYS64T256020HU–3.7–A HYS72T256020HU–3.7–A 2 GByte 2 GByte ×64 ×72 2 Ranks (×8) 2 Ranks (×8) PC2–4200U–444 PC2–4200E–444 Rev ...

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... RRD.MIN t 29 [ns] RCD.MIN Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules SPD codes for HYS64T256020HU–5–A HYS64T256020HU–5–A HYS72T256020HU–5–A 2 GByte 2 GByte ×64 ×72 2 Ranks (×8) 2 Ranks (×8) PC2–3200U–333 PC2–3200E–333 Rev ...

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... T 57 (DT7 Psi(ca) PLL 59 Psi(ca) REG ∆ (DTPLL) PLL ∆ (DTREG) / Toggle Rate REG 62 SPD Revision Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS64T256020HU–5–A 2 GByte ×64 2 Ranks (×8) PC2–3200U–333 Rev. 1.1 HEX ...

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... Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules HYS64T256020HU–5–A HYS72T256020HU–5–A 2 GByte 2 GByte ×64 ×72 2 Ranks (×8) 2 Ranks (×8) PC2–3200U–333 PC2– ...

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... Description 99 - 127 Not used 128 - Blank for customer use 255 Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules HYS64T256020HU–5–A HYS72T256020HU–5–A 2 GByte 2 GByte ×64 ×72 2 Ranks (×8) 2 Ranks (×8) PC2–3200U–333 PC2–3200E–333 Rev ...

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... Package Outlines Notes 1. The chip is only found on ECC modules. 2. General tolerances +/- 0.15 3. Drawing according to ISO 8015 Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Package Outline Raw Card B L-DIM-240-2 55 Internet Data Sheet FIGURE 6 ...

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... Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015 Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Package Outline Raw Card G L-DIM-240-7 56 Internet Data Sheet FIGURE 7 ...

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... Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015 Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules Package Outline L-DIM-240-9 57 Internet Data Sheet FIGURE 8 ...

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... DRAMs and DIMMs) Qimonda’s nomenclature uses simple coding combined with some propriatory coding. and component product type number as well as the field number. The detailed field description together with possible values and coding explanation is listed for modules in Example for Field Number ...

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... Field Description 10 Speed Grade 11 Die Revision 1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column “Coding”. Field Description 1 Qimonda Component Prefix ...

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... Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.2 AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.3 ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.4 I Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6 Product Type Nomenclature (DDR2 DRAMs and DIMMs Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Rev. 1.32, 2006-09 03062006-5RK8-1X8J HYS[64/72]T256xxxHU–[3/…/5]–A Unbuffered DDR2 SDRAM Modules 60 Internet Data Sheet ...

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Edition 2006-09 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...