HYS64T256020HU-3-A QIMONDA [Qimonda AG], HYS64T256020HU-3-A Datasheet - Page 22

• Manufacturer Part Number: HYS64T256020HU-3-A
• Description: 240-Pin Unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1) For details and notes see the relevant Qimonda component data sheet
2)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
Rev. 1.32, 2006-09
03062006-5RK8-1X8J
Parameter
Active to active command period for 1KB page
size products
Active to active command period for 2KB page
size products
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
Write recovery time
Auto-Precharge write recovery + precharge time
Internal write to read command delay
Internal Read to Precharge command delay
Exit self-refresh to a non-read command
Exit self-refresh to read command
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
CKE minimum pulse width ( high and low pulse
width)
ODT turn-on delay
ODT turn-on
ODT turn-on (Power down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power down mode)
ODT to power down entry latency
ODT to power down exit latency
Mode register set command cycle time
MRS command to ODT update delay
OCD drive mode output delay
Minimum time clocks remain ON after CKE
asynchronously drops LOW
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode.
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V. See notes
5)6)7)8)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RRD
RRD
FAW
FAW
CCD
WR
DAL
WTR
RTP
XSNR
XSRD
XP
XARD
XARDS
CKE
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
MRD
MOD
OIT
DELAY
22
DDR2–667
7.5
10
37.5
50
2
15
WR +
7.5
7.5
t
200
2
2
7 – AL
3
2
t
t
2.5
t
t
3
8
2
0
0
t
t
Min.
RFC
AC.MIN
AC.MIN
AC.MIN
AC.MIN
LS
LH
+
+10
t
CK .AVG
t
+ 2
+ 2
nRP
+
—
—
—
—
—
—
—
—
—
2
2.5
––
—
12
12
Max.
—
—
—
—
—
—
t
2 x
t
t
2.5 x
t
––
AC.MAX
AC.MAX
AC.MAX
AC.MAX
Unbuffered DDR2 SDRAM Modules
HYS[64/72]T256xxxHU–[3/…/5]–A
t
CK.AVG
t
CK.AVG
+ 0.7
+ 1
+ 0.6
+ 1
+
+
Unit
ns
ns
ns
ns
nCK
ns
nCK
ns
ns
ns
nCK
nCK
nCK
nCK
nCK
nCK
ns
ns
nCK
ns
ns
nCK
nCK
nCK
ns
ns
ns
Internet Data Sheet
Note
8)
28)
28)
28)
28)
28)
29)30)
28)31)
28)
28)
32)
9)33)
34)35)
28)
28)
1)2)3)4)5)6)7)