HYS64T256020HU-3-A QIMONDA [Qimonda AG], HYS64T256020HU-3-A Datasheet - Page 18

• Manufacturer Part Number: HYS64T256020HU-3-A
• Description: 240-Pin Unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

3.3
3.3.1
List of speed grade definition tables.
•
•
•
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
Rev. 1.32, 2006-09
03062006-5RK8-1X8J
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Table 14 “Speed Grade Definition Speed Bins for DDR2–667” on Page 18
Table 15 “Speed Grade Definition Speed Bins for DDR2–533C” on Page 19
Table 16 “Speed Grade Definition Speed Bins for DDR2–400B” on Page 20
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
input reference level is the crosspoint when in differential strobe mode
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
AC Characteristics
Speed Grade Definitions
@ CL = 3
@ CL = 4
@ CL = 5
V
REF
Symbol
t
t
t
t
t
t
t
V
CK
CK
CK
RAS
RC
RCD
RP
stabilizes. During the period before
TT
.
DDR2–667C
–3
4–4–4
Min.
5
3
3
45
57
12
12
18
Speed Grade Definition Speed Bins for DDR2–667
8
8
8
70000
—
—
—
Max.
V
REF
DDR2–667D
–3S
5–5–5
Min.
5
3.75
3
45
60
15
15
stabilizes, CKE = 0.2 x
Unbuffered DDR2 SDRAM Modules
HYS[64/72]T256xxxHU–[3/…/5]–A
Max.
8
8
8
70000
—
—
—
V
DDQ
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
CK
Internet Data Sheet
is recognized as low.
TABLE 14
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
t
REFI
.