GS881E18T GSI [GSI Technology], GS881E18T Datasheet
GS881E18T
Related parts for GS881E18T
GS881E18T Summary of contents
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... DD Functional Description Applications The GS881E18//36T is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. ...
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GS881E18 100-Pin TQFP Pinout 100 DDQ ...
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GS881E36 100-Pin TQFP Pinout 100 DDQ ...
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TQFP Pin Descriptio Pin Location 37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 ...
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Pin Location 15, 41, 65, 91 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76 11, 20, 27, 54, 61, 70, 77 Rev: 1.10 9/2000 Specifications cited are subject to change ...
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GS881E18/36 Block Diagram Register A0– LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown for ...
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... ByteSafe™ Parity Functions This SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are reported one clock cycle later ...
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Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control ByteSafe Data Parity Control Note: There are pull-up devices on the LBO, DP and FT pins and a pull down device on the ZZ pin, so ...
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Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...
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Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...
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Simplified State Diagram Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1 and E2) and Write ...
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Simplified State Diagram with G Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make ...
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Absolute Maximum Ratings (All voltages reference Symbol Description V Voltage Voltage in V DDQ DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V Voltage on Other ...
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... Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP) Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper- ature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1 ...
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AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
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Operating Currents Parameter Test Conditions Symbol Device Selected; Operating Pipeline All other inputs Current Output open Flow-Thru Standby Pipeline 0.2V DD Current Flow-Thru Device Deselected; Deselect Pipeline All other inputs Current V ...
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AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Clock to Output Valid Flow- Thru Clock to Output Invalid Clock to Output in Low-Z Clock ...
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Write Cycle Timing Single Write ADSP ADSC ADV – WR1 – Hi-Z DQ – Rev: 1.10 ...
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Flow Through Read Cycle Timing Single Read ADSP ADSC tS ADV –A RD1 – tOE G tOLZ ...
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Flow Through Read-Write Cycle Timing Single Read ADSP ADSC ADV – RD1 – tOE G tKQ Hi-Z DQ –DQ ...
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Pipelined DCD Read Cycle Timing Single Read ADSP ADSC ADV –A RD1 – Hi-Z DQ – ...
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Pipelined DCD Read-Write Cycle Timing Single Read ADSP ADSC tS tH ADV – RD1 – Hi-Z DQ ...
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... Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention ...
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JTAG Pin Descriptions Pin Pin Name I/O Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the TCK Test Clock In falling edge of TCK. Test Mode The TMS input ...
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JTAG TAP Block Diagram TDI TMS TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command ...
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TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for ...
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EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, ...
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JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Test Port Input High Voltage Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output ...
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JTAG Port Timing Diagram tTKL tTKH TCK TMS TDI TDO tTKQ JTAG Port AC Electrical Characteristics Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI ...
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GS811E18/36T TQFP Boundary Scan Register Order x36 x18 Pin n n ...
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Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 0.0 -20.0 -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0 Rev: 1.10 9/2000 Specifications cited are subject to change without notice. For ...
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TQFP Package Drawing Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e ...
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... GS881E36T-66I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS881E18TT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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Revision History Types of Changes DS/DateRev. Code: Old; Format or Content New GS881E18/36TRev1.04h 5/ 1999; 1.05 9/1999I GS881E18/36T1.05 9/ 1999I;1.05 11/1999J GS881E18/36T1.05 11/ 1999K881E18/36T1.06 1/ 200010L GS881E18/36T1.06 1/ 2000L; GS881E18/36T1.07 3/ 2000N; GS881E18/36T1.07 3/ 2000N; GS881E18/36T1.08 3/ 2000O; 881E GS881E18/36T1.08 ...