GS881E18T GSI [GSI Technology], GS881E18T Datasheet - Page 7

• Manufacturer Part Number: GS881E18T
• Description: 512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
• Manufacturer: GSI [GSI Technology]

ByteSafe™ Parity Functions
This SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow
Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are
reported one clock cycle later. (See Write Parity Error Output Timing Diagram.) The Data Parity Mode (DP) pin must be tied
high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data.
Validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a
parity error. Multiple Parity Error Output pins may share a common pull-up resistor.
Write Parity Error Output Timing Diagram
Rev: 1.10 9/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
CK
QE
DQ
QE
DQ
D In A
D In A
tLZ
tKQ
D In B
D In B
Err A
7/34
tKQX
tLZ
tKQ
tHZ
D In C
D In C
Err A
tKQX
tHZ
D In D
D In D
Err C
GS881E18/36T-11/11.5/100/80/66
D In E
D In E
Err C
© 2000, Giga Semiconductor, Inc.
Preliminary
BPR 1999.05.18