PPC405EX-NPAFFFTX AMCC [Applied Micro Circuits Corporation], PPC405EX-NPAFFFTX Datasheet
PPC405EX-NPAFFFTX
Related parts for PPC405EX-NPAFFFTX
PPC405EX-NPAFFFTX Summary of contents
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PowerPC 405EX Embedded Processor Features ® • AMCC PowerPC 405 32-bit RISC processor core operating from 333MHz to 667MHz including 16KB I- and D-caches with parity checking • On-chip 128-bit processor local bus (PLB) operating up to 200MHz • ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power PC 405 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 USB 2.0 OTG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DDR1/2 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PCI Express ...
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... PPC405EX – PowerPC 405EX Embedded Processor List of Figures Figure 1. PPC405EX Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Package 27mm, 388-Ball EPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3. Clocking Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 4. Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 5. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 6. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 7 ...
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... This section provides the part number nomenclature. For availability, contact your local AMCC sales office. Order Part Number Product Name (see Notes:) PPC405EX PPC405EX-SpAfffTx PPC405EX PPC405EX-NpAfffTx Notes security feature present security feature not present Package lead-free (RoHS compliant leaded Chip revision level A 4. fff = Processor frequency 333 = 333MHz ...
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... DDR1/2 EIP-94 SDRAM Security Controller Feature The PPC405EX is designed using the IBM Microelectronics Blue Logic blocks are integrated together to create an ASIC (application-specific integrated circuit) product. This approach provides a consistent way to create complex ASICs using IBM CoreConnect AMCC Proprietary DCRs SCP IICx2/ ...
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... PPC405EX – PowerPC 405EX Embedded Processor Address Maps The PPC405EX incorporates two address maps. The first address map defines the possible use of addressable memory regions that the processor can access. The second address map defines Device Configuration Register (DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EX processor through the use of mtdcr and mfdcr instructions ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 2. DCR Address Map Function 1 Total DCR Address Space Reserved CPR (Clocking, Power-on Reset) System DCRs DDR 1/2 SDRAM Controller External Bus Controller (EBC) External Bus Master (EBM) Reserved PLB4XAHB Bridge Reserved PCI Express 0 PCI Express 1 ...
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... Selectable processor vs. bus clock ratios (N:1 ratio only, where N = Internal Buses The PPC405EX contains four internal buses: the processor local bus (PLB), the Advanced High-Performance Bus (AHB), the on-chip peripheral bus (OPB), and the device control register (DCR) bus. High performance devices such as the processor, the DDR SDRAM memory controller, PCI Express, the Ethernet MAL, and DMA utilize the PLB ...
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... PPC405EX – PowerPC 405EX Embedded Processor OPB The OPB provides 32-bit address and data interfaces, and operates up to 100MHz. There are bridges between the OPB and the PLB. Features include: • Pipelined read support • Dynamic bus sizing • Single-cycle data transfer between masters and slaves ...
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... Features include: • Compliant with PCI Express base specification 1.1 • Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream) – Applications compliant with MSI rules are limited to one End Point port per PPC405EX 10 Revision 1.09 - August 21, 2007 Preliminary Data Sheet ...
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... PPC405EX – PowerPC 405EX Embedded Processor • PCI-Express to PCI-Express opaque (Non-Transparent) bridge • Power Management • Supports one virtual channel (VC0) with no Traffic Class (TC) filtering • Maximum Payload block size 256B • Supports up to 512B maximum Read request size • Requests supported: – ...
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... PPC405EX – PowerPC 405EX Embedded Processor • Media Access Control Security (MACSec) features – Cipher suite GCM-AES-128 – Header insertion and removal – Integrity and confidentiality with MSDU • SGT L2 supported features: – GCM-AES with 128-bit key. – Integrity only and with confidentiality of MSDU • ...
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... PPC405EX – PowerPC 405EX Embedded Processor • Independently controlled transmit, receive, line status, and data set interrupts • Programmable baud generator (divides serial clock input and generates 16x clock) • Ability to add/delete standard asynchronous communication bits such as start, stop, and parity to/from serial data • ...
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... PPC405EX – PowerPC 405EX Embedded Processor General Purpose I/O (GPIO) Controller The GPIO controller enables multiplexing of module I/O pins with multiple functions within the chip. That is, a single package pin can be assigned to multiple I/O functions. Which function the pin is assigned to is determined by register bit settings controlled by software. This significantly reduces the number of package pins needed to support multiple I/O groups ...
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... PPC405EX – PowerPC 405EX Embedded Processor • Programmable internal/external loopback capabilities • OPB slave (MAC) and PLB master (MAL) interfaces are 32 bits wide • Extensive error/status vector generation for each processed packet • VLAN tag ID supported (according to IEEE Draft 802.3ac/D1.0 standard) • ...
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... PPC405EX – PowerPC 405EX Embedded Processor Figure 2. Package 27mm, 388-Ball EPBGA Gold Gate Release Corresponds to A01 Ball Location Top View Epoxy Mold Compound Side View PCB Substrate Bottom View 27 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Signal Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Shared signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 2 of 13) Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 EAGND EAV DD ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EOV DD EOV DD EOV DD EOV DD EOV DD EOV DD [ExtAck]GPIO25[DMAAck3][IRQ3] [ExtReq]GPIO24[DMAEOT2][IRQ4] ExtReset 18 Revision 1.09 - August 21, 2007 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 3 of 13) Signal Name GMCCD, GMC1RxClk GMCCrS, GMC1TxClk GMCGTxClk, GMC0TxClk GMCMDClk GMCMDIO GMCRefClk GMCRxClk, GMC0RxClk GMCRxD0, GMC0RxD0 GMCRxD1, GMC0RxD1 GMCRxD2, GMC0RxD2 GMCRxD3, GMC0RxD3 GMCRxD4, GMC1RxD0 GMCRxD5, GMC1RxD1 GMCRxD6, GMC1RxD2 GMCRxD7, GMC1RxD3 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 4 of 13) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 5 of 13) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 6 of 13) Signal Name GPIO00[PerDataPar0] GPIO01[PerDataPar1] GPIO02[PerDataPar2] GPIO03[PerDataPar3] GPIO04[PerData20][USB2Data4] GPIO05[PerData21][USB2Data5] GPIO06[PerData22][USB2Data6] GPIO07[PerData23][USB2Data7] GPIO08[PerCS1][NFCE1][IRQ7] GPIO09[PerCS2][NFCE2][IRQ8] GPIO10[PerCS3][NFCE3][IRQ9] GPIO11[IRQ6] GPIO12[PerData16][USB2Data0] GPIO13[PerData17][USB2Data1] GPIO14[PerData18][USB2Data2] ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 7 of 13) Signal Name [IRQ0]GPIO31[DMAAck1] [IRQ1]GPIO30[DMAReq1] [IRQ2]GPIO29[DMAEOT1] [IRQ3][ExtAck]GPIO25[DMAAck3] [IRQ4][ExtReq]GPIO24[DMAEOT2] [IRQ5][BusReq]GPIO27[DMAEOT3] [IRQ6]GPIO11 [IRQ7][PerCS1][NFCE1]GPIO08 [IRQ8][PerCS2][NFCE2]GPIO09 [IRQ9][PerCS3][NFCE3]GPIO10 MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 8 of 13) Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 9 of 13) Signal Name [NFALE]PerData30 [NFCE0]PerCS0 [NFCE1][PerCS1]GPIO08[IRQ7] [NFCE2][PerCS2]GPIO09[IRQ8] [NFCE3][PerCS3]GPIO10[IRQ9] [NFCLE]PerData29 [NFData00]PerData00 [NFData01]PerData01 [NFData02]PerData02 [NFData03]PerData03 [NFData04]PerData04 [NFData05]PerData05 [NFData06]PerData06 [NFData07]PerData07 [NFData08]PerData08 [NFData09]PerData09 [NFData10]PerData10 [NFData11]PerData11 [NFData12]PerData12 [NFData13]PerData13 [NFData14]PerData14 [NFData15]PerData15 [NFRdyBusy]PerData31 [NFREn]PerData27 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 10 of 13) Signal Name PCIE0ATB PCIE0ClkC PCIE0ClkT PCIE0RExt PCIE0RExtG PCIE0Rx PCIE0Rx PCIE0Tx PCIE0Tx PCIE1ATB PCIE1ClkC PCIE1ClkT PCIE1RExt PCIE1RExtG PCIE1Rx PCIE1Rx PCIE1Tx PCIE1Tx [PerAddr05]GPIO26[TS3][DMAEOT0] PerAddr06[TS2][DMAReq0] PerAddr07[TS1][DMAAck0] PerAddr08[TS0][DMAReq3] PerAddr09[TS1E] ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 11 of 13) Signal Name PerCS0[NFCE0] [PerCS1][NFCE1]GPIO08[IRQ7] [PerCS2][NFCE2]GPIO09[IRQ8] [PerCS3][NFCE3]GPIO10[IRQ9] PerData00[NFData00] PerData01[NFData01] PerData02[NFData02] PerData03[NFData03] PerData04[NFData04] PerData05[NFData05] PerData06[NFData06] PerData07[NFData07] PerData08[NFData08] PerData09[NFData09] PerData10[NFData10] PerData11[NFData11] PerData12[NFData12] PerData13[NFData13] PerData14[NFData14] PerData15[NFData15] [PerData16]GPIO12[USB2Data0] [PerData17]GPIO13[USB2Data1] [PerData18]GPIO14[USB2Data2] [PerData19]GPIO15[USB2Data3] ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 12 of 13) Signal Name PSROUser RAS Reserved SAGND SAV DD [SCPClkOut]IIC1SClk SCPDI [SCPDO]IIC1SData VREF S 1B VREF S 2A VREF S 2B VREF SysClk ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 13 of 13) Signal Name [UART0CTS]GPIO18 [UART0DCD][UART1CTS]GPIO16 [UART0DSR][UART1RTS]GPIO17 [UART0DTR][UART1Tx]GPIO20 [UART0RI][UART1Rx]GPIO21 [UART0RTS]GPIO19 UART0Rx UART0Tx [UART1CTS][UART0DCD]GPIO16 [UART1RTS][UART0DSR]GPIO17 [UART1Rx][UART0RI]GPIO21 [UART1Tx][UART0DTR]GPIO20 UARTSerClk USB2Clk [USB2Data0][PerData16]GPIO12 [USB2Data1][PerData17]GPIO13 [USB2Data2][PerData18]GPIO14 ...
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... PPC405EX – PowerPC 405EX Embedded Processor In the following table, only the default signal name is shown for each ball. Shared balls are marked with an asterisk (*). To determine what signals or functions are shared on those balls, look up the default signal name in “Signals Listed Alphabetically” on page 17. The following table lists the signals by ball assignment. ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball E01 GND F01 E02 UARTSerClk F02 E03 GND F03 OV E04 F04 DD E05 No ball F05 E06 No ball F06 E07 No ball F07 E08 No ball F08 E09 No ball F09 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball J01 PCIE0Rx K01 J02 PCIE0Rx K02 AV J03 K03 DD J04 GND K04 J05 No ball K05 J06 No ball K06 J07 No ball K07 J08 No ball K08 J09 No ball K09 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball N01 PCIE1Rx P01 N02 PCIE1Rx P02 AV N03 P03 DD AV N04 P04 DD N05 No ball P05 N06 No ball P06 N07 No ball P07 N08 No ball P08 N09 No ball P09 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball U01 GND V01 U02 GND V02 U03 GPIO28 V03 V U04 V04 DD U05 No ball V05 U06 No ball V06 U07 No ball V07 U08 No ball V08 U09 No ball V09 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball AA01 IIC0SData AB01 AA02 IIC1SClk * AB02 AA03 SCPDI AB03 AA04 IIC1SData * AB04 AA05 No ball AB05 AA06 No ball AB06 AA07 No ball AB07 AA08 No ball AB08 AA09 No ball ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball AE01 GMCTxD0 * AF01 AE02 GND AF02 AE03 GMCMDClk AF03 AE04 GMCGTxClk * AF04 AE05 GMCRxDV * AF05 AE06 GMCRxD7 * AF06 AE07 EAGND AF07 EAV AE08 AF08 DD AE09 GMCRxD4 * ...
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... PPC405EX – PowerPC 405EX Embedded Processor Pin Group List The following table provides a summary of the number of package pins (balls) associated with each functional interface group. Table 5. Pin Groups Total Signal Pins Total Power Pins In the table “Signal Functional Description” on page 38, each external signal is listed along with a short description of the signal function. Active-low signals (for example, Halt) are marked with an overline. See the preceding table, “ ...
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... PPC405EX – PowerPC 405EX Embedded Processor Signal Functional Descriptions The following table provides a description of the I/O signals on the PPC405EX. Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. ...
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... Test clock. TDI Test data in. TDO Test data out. TMS Test mode select. Test reset. Must be low at power-on to initialize the JTAG controller TRST and for normal operation of the PPC405EX. AMCC Proprietary Revision 1.09 - August 21, 2007 Preliminary Data Sheet Description I/O Type Notes O CML ...
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... Signal Name System Interface SysClk System input clock. SysErr Machine check exception has occurred. Main system reset. This signal may be driven by the PPC405EX to SysReset cause a board level reset to occur. TestEn Test enable. Reserved for manufacturing LSSD test. Halt External request to stop the processor. ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. ...
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... Case Temperature Range under bias Junction Temperature Range 1. The analog voltages can be derived from the +1.2V and +2.5V supplies, but must be filtered as shown below before entering the PPC405EX. Use a separate filter for each voltage. This circuit can be used for AV AGND with AV and AHV ...
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... PPC405EX – PowerPC 405EX Embedded Processor Thermal Management Table 8. Package Thermal Specifications The PPC405EX is designed to operate within a case temperature range Conditions” on page 47. Thermal resistance values for the EPBGA packages in a convection environment are as follows: Parameter Symbol Junction-to-ambient θ thermal resistance ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 9. Recommended DC Operating Conditions (Sheet Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter Logic Supply Voltage I/O Supply Voltage SDRAM DDR1(2) Supply Voltage CMOS Supply Voltage ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 9. Recommended DC Operating Conditions (Sheet Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter I/O Maximum Allowable Overshoot (3.3V LVTTL) I/O Maximum Allowable Undershoot (3.3V LVTTL) Case Temperature Notes: 1. LPDL is least positive down level ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 11. Typical DC Power Supply Requirements with DDR1 SDRAM Frequency (MHz) +1.2V 333 1.15 400 1.25 533 1.25 667 1.27 Notes: 1. Values are estimates and subject to change. 2. DDR1 running at 333MHz., PLB running at 166MHz. 3. DDR1 running at 400MHz., PLB running at 200MHz. 4. DDR1 running at 355MHz., PLB running at 177MHz. ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 14. DC Power Supply Loads with DDR2 SDRAM Parameter V (+1.2V) active operating current DD AV (+1.2V) active operating current DD AHV (+2.5V) active operating current DD OV (+3.3V) active operating current DD SV (+1.8V) active operating current DD EOV (+2.5V) active operating current DD SAV (+2.5V) active operating current ...
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... PPC405EX – PowerPC 405EX Embedded Processor Figure 3. Clocking Waveform Note: SysClk and GMCRefClk are 2.5V (3.3V tolerant) signals. Rise time should be measured between 0.7V and 1.7V AMCC Proprietary Revision 1.09 - August 21, 2007 Preliminary Data Sheet 1.7 (2.0) V 1.25 (1.5) V 0.7 (0. ...
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... PPC405EX – PowerPC 405EX Embedded Processor Spread Spectrum Clocking Care must be taken if using a spread spectrum clock generator (SSCG) with the PPC405EX. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is called tracking skew ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 16. Peripheral Interface I/O Clock Timings Clock GMCTxClk frequency GMCTxClk high time GMCTxClk low time GMCRxClk frequency GMCRxClk high time GMCRxClk low time GMCGTxClk GMCMDClk GMCRefClk GMCRefClk edge stability (phase jitter, cycle-to-cycle) GMCRefClk rise time ...
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... PPC405EX – PowerPC 405EX Embedded Processor Figure 4. Input Setup and Hold Timing Waveform 1.25 (1.5)V Clock Inputs 1.25 (1.5)V Figure 5. Output Delay and Float Timing Waveform Clock 1.25 (1.5 MAX Outputs 1.25 (1.5 MIN Outputs 1.25 (1.5 MIN MIN Valid Valid MAX 1.25 (1.5)V Revision 1.09 - August 21, 2007 Preliminary Data Sheet ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 17. I/O Specifications—All CPU Speeds (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Input (ns) Signal Setup Time Hold Time (T min PCI Express Interface PCIEnATB PCIEnRx PCIEnRx PCIEnTx PCIEnTx Ethernet GMII Interface GMCCD 2 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 17. I/O Specifications—All CPU Speeds (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Input (ns) Signal Setup Time Hold Time (T min JTAG Interface TCK TDI TDO TMS TRST System Interface GPIO00:10 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 18. I/O Specifications—333 MHz to 667 MHz CPU Notes: 1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns. Input (ns) Signal Setup Time Hold Time (T min) IS External Peripheral Interface PerClk PerAddr05:31 2 ...
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... In a typical system, users advance MemClkOut by 90°. This depends on the specific application and requires a thorough understanding of the memory system in general (refer to the DDR SDRAM Controller chapter in the PPC405EX Embedded Processor User’s Manual). The signals are terminated as indicated in Figure 6 for the DDR timing data in the following sections. ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 19. DDR SDRAM Output Driver Specifications Signal Path Write Data MemData00:31 ECC0:7 DM0:4 MemClkOut MemAddr00:14 BA0:2 RAS CAS WE BankSel0:1 MemClkEn DQS0:4 MemODT0:1 DDR SDRAM Write Operation The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes. The following data is generated by means of simulation and includes logic, driver, package RLC, and lengths ...
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... PPC405EX – PowerPC 405EX Embedded Processor The following diagram illustrates the relationship among the signals involved with a DDR write operation. Figure 7. DDR SDRAM Write Cycle Timing PLB Clk MemClkOut Addr/Cmd DQS MemData T = Delay from rising edge of MemClkOut to rising/falling edge of signal (skew) ...
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... The Read of the incoming Data from the SDRAM is done on the rising and falling edges of the differential DQS signal. The Data must be centered to these edges for correct operation. The PPC405EX can delay with very fine granularity the DQS through register programming. DDR SDRAM MemClkOut0 and Read Clock Delay In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency ...
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... PPC405EX – PowerPC 405EX Embedded Processor Figure 8. DDR SDRAM Read Data Path Ext FeedBack Signals Driver MemDCFdbkD Coarse Delay Rec Fine Delay MemDCFdbkR DQS aligned FBK signal Feedback Data Capture Window Package Mux pins FF DQS Rising Edge Sync DQ Data Stage 1 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Table 24. I/O Timing—DDR SDRAM Read Timing and T are measured under worst case conditions Clock speed for the values in the table is 200MHz. 3. The time values in the table include 1 cycle at 200MHz (5ns x 0.25 = 1.25 ns obtain adjusted T and T values for lower clock frequencies, subtract 0 ...
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... PPC405EX – PowerPC 405EX Embedded Processor Figure 10. DDR SDRAM Read Cycle Timing—Example DDR 1X Clock DDR 2X Clock Memclk (Diff.) DQS at MemCntl Pin Data at Pin Feedback Output DDR 1X Clock cycle Delayed DQS Data Out Stage 1 (0) Data Out Stage 1 (1) Data out Stage 1 (2) ...
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... EBC 8-bit wide NAND Flash IIC ROM at address 0xA8 EBC 8-bit wide ROM IIC ROM at address 0xA4 Note: See the PPC405EX Embedded Processor User’s Manual for option descriptions and other details regarding the boot process. AMCC Proprietary Revision 1.09 - August 21, 2007 Preliminary Data Sheet ...
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... PPC405EX – PowerPC 405EX Embedded Processor Revision Log Date Version 02/27/2007 1.00 03/01/2007 1.01 03/22/2007 1.02 04/24/2007 1.03 05/24/2007 1.04 06/04/2007 1.05 06/07/2007 1.06 06/28/2007 1.07 07/12/2007 1.08 08/21/2007 1.09 66 Contents of Modification Initial creation of document. Updates following review of initial document. Change package drawing to eliminate confusion. Expand system memory map. Define FSource0 signal as Reserved. ...
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... PPC405EX – PowerPC 405EX Embedded Processor 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC’ ...