PPC405EX-NPAFFFTX AMCC [Applied Micro Circuits Corporation], PPC405EX-NPAFFFTX Datasheet - Page 62

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PPC405EX-NPAFFFTX

Manufacturer Part Number
PPC405EX-NPAFFFTX
Description
PowerPC 405EX Embedded Processor
Manufacturer
AMCC [Applied Micro Circuits Corporation]
Datasheet
PPC405EX – PowerPC 405EX Embedded Processor
Figure 8. DDR SDRAM Read Data Path
DDR SDRAM Read Cycle Timing
The following diagram illustrates the relationship of the signals involved with a DDR read operation.
Figure 9. DDR SDRAM Memory Data and DQS
62
MemDCFdbkR
Ext FeedBack
Signals
MemDCFdbkD
Package
pins
DQ
Data
(x32)
DQS
Programmed
Rec
Read DQS
Mux
Delay
Driver
0
Feedback
Data Capture
Window
1
Coarse Delay
MemData
Fine Delay
DQS
Stage 1
FF
FF
7
DQS Falling
Edge Sync
DQS Rising
Edge Sync
DQS aligned
FBK signal
0
2
4
6
1
3
5
7
T
T
SD
HD
Mux
DDR 1X Clock
D
D
DDR 1X Clock
DDR 1X Clock
FeedBack
Signal Gen
Stage 2
Stage 2 Store
Cycles
Delay
FF
FF
FF
FF
T1 T2 T3 T4
C
C
Q2_Ovs
Q2
(x32)
(x32)
+1
CAS Lat Delay
Compare
adjust
Oversampling
Fine Delay
Read FIFO
Upper
Lower
Read Start
Preliminary Data Sheet
Oversampling
Clock
Revision 1.09 - August 21, 2007
Read Latency adjust circuit
PLB 1X Clock
Stage 3
FF
Q3
FF: Flip-Flop
AMCC Proprietary
PLB bus
[0:63]
PLB bus
[64:127]

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