PPC405EX-NPAFFFTX AMCC [Applied Micro Circuits Corporation], PPC405EX-NPAFFFTX Datasheet - Page 60

• Manufacturer Part Number: PPC405EX-NPAFFFTX
• Description: PowerPC 405EX Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

PPC405EX – PowerPC 405EX Embedded Processor
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 7. DDR SDRAM Write Cycle Timing
Note: The timing data in the following tables is based on simulation runs using Einstimer.
Table 21. I/O Timing—DDR SDRAM T
Notes:
1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle.
2. Clock speed is 200MHz.
60
DQS0
DQS1
DQS2
DQS3
DQS4
Signal Name
MemClkOut
T
T
T
T
T
T
SK
SA
SD
HD
HA
DS
MemData
PLB Clk
= Delay from rising edge of MemClkOut to rising/falling edge of signal (skew)
= Setup time for address and command signals to MemClkOut
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Hold time for address and command signals from MemClkOut
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
DQS
Addr/Cmd
DS
T
SA
T
SK
T
HA
Minimum
T
4
4
4
4
4
T
SD
DS
T
HD
T
DS
T
DS
(ns)
T
SD
Preliminary Data Sheet
T
Revision 1.09 - August 21, 2007
HD
Maximum
6
6
6
6
6
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