LIS331DL_08 STMICROELECTRONICS [STMicroelectronics], LIS331DL_08 Datasheet - Page 28
LIS331DL_08
Manufacturer Part Number
LIS331DL_08
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.LIS331DL_08.pdf
(42 pages)
- Current page: 28 of 42
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Register description
7.4
7.5
28/42
Table 21.
CTRL_REG3 [interrupt CTRL register] (22h)
Table 22.
Table 23.
Table 24.
HP_FILTER_RESET (23h)
Dummy register. Reading at this address zeroes instantaneously the content of the internal
high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0 g.
This allows to overcome the settling time of the high pass filter.
IHL
PP_OD
I2_CFG2
I2_CFG1
I2_CFG0
I1_CFG2
I1_CFG1
I1_CFG0
IHL
I1(2)_CFG2
HPcoeff2,1
00
01
10
11
0
0
0
0
1
1
High pass filter cut-off frequency configuration
CTRL_REG3 register
CTRL_REG3 description
Data Signal on INT1(2) pad control bits
PP_OD
Interrupt active high, low. Default value 0.
(0: active high; 1: active low)
Push-pull/Open Drain selection on interrupt pad. Default value 0.
(0: push-pull; 1: open drain)
Data signal on INT2 pad control bits. Default value 000.
(see table below)
Data signal on INT1 pad control bits. Default value 000.
(see table below)
I1(2)_CFG1
I2_CFG2
0
0
1
1
0
1
(ODR=100 Hz)
ft (Hz)
I2_CFG1
0.25
0.5
2
1
I1(2)_CFG0
I2_CFG0
0
1
0
1
0
1
I1_CFG2
FF_WU_1 OR FF_WU_2
(ODR=400 Hz)
Click interrupt
INT 1(2) Pad
I1_CFG1
Data ready
FF_WU_1
FF_WU_2
ft (Hz)
GND
8
4
2
1
LIS331DL
I1_CFG0
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