LIS331DL_08 STMICROELECTRONICS [STMicroelectronics], LIS331DL_08 Datasheet - Page 31

• Manufacturer Part Number: LIS331DL_08
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

LIS331DL
7.11
7.12
FF_WU_SRC_1 (31h)
Table 32.
Table 33.
Free-fall and wake-up source register. Read only register.
Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt and
allows the refreshment of data in the FF_WU_SRC_1 register if the latched option was
chosen.
FF_WU_THS_1 (32h)
Table 34.
Table 35.
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If
DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration
counter is decremented.
IA
ZH
ZL
YH
YL
XH
XL
THS6, THS0
DCRM
--
DCRM
Interrupt Active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
Z High. Default value: 0
(0: no interrupt, 1: Z High event has occurred)
Z Low. Default value: 0
(0: no interrupt; 1: Z Low event has occurred)
Y High. Default value: 0
(0: no interrupt, 1: Y High event has occurred)
Y Low. Default value: 0
(0: no interrupt, 1: Y Low event has occurred)
X High. Default value: 0
(0: no interrupt, 1: X High event has occurred)
X Low. Default value: 0
(0: no interrupt, 1: X Low event has occurred)
FF_WU_SRC_1 register
FF_WU_SRC_1 description
FF_WU_THS_1 register
FF_WU_THS_1 description
THS6
IA
Resetting mode selection. Default value: 0
(0: counter reset; 1: counter decremented)
Free-fall / wake-up Threshold: default value: 000 0000
THS5
ZH
THS4
ZL
THS3
YH
THS2
YL
Register description
THS1
XH
THS0
XL
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