ELANSC310 AMD [Advanced Micro Devices], ELANSC310 Datasheet - Page 30

• Manufacturer Part Number: ELANSC310
• Description: Single-Chip, 32-Bit, PC/AT Microcontroller
• Manufacturer: AMD [Advanced Micro Devices]

PIN DESCRIPTIONS
Descriptions of the ÉlanSC310 microcontroller pins are
organized into the following functional groupings:
MEMORY BUS INTERFACE
CAS1H [SRCS3], CAS1L [SRCS2],
CAS0H [SRCS1], CAS0L [SRCS0]
Column Address Strobe (Outputs; Active Low)
Column Address Strobe indicates to DRAM that a valid
column address is present on the MA10–MA0 lines.
Two CAS signals are allocated to each 16-bit bank, one
per byte.
When SRAM, instead of DRAM, is configured as main
memory, SRCS3, SRCS2, SRCS1, and SRCS0 are the
alternate pin functions corresponding to CAS1H,
CAS1L
lects a byte in one of two possible 16 bit wide SRAM
banks. The SRAM functionality is selected via firm-
ware. In this mode, all four of these outputs are active
Low. For more information about
page 41.
DOSCS
DOS ROM Chip Select (Output; Active Low)
The DOS ROM Chip Select is an active Low output that
provides the chip select function for the Flash/ROM
array banks that are used to hold the operating system
or application code. DOSCS is used to select the DOS
ROMs and can be configured to respond to direct ad-
dressing or Memory Management System (MMS) ad-
dressing.
MA11–MA0/SA23–SA12
Memory Address (Outputs; Active High)
Memory address lines for multiplexed and nonmulti-
plexed memory devices; their effect depends on the
system configuration and the type of bus cycle.
30
Memory bus interface
System interface
Keyboard interface
Parallel port interface
Serial port interface
When the system is configured as DRAM, the
MA10–MA0 signals are multiplexed outputs and
convey the row address during RAS assertion and
column address during CAS assertion.
When system memory is configured as SRAM,
MA11–MA0 output the system addresses, SA12–
SA23, and are used in conjunction with SA1–SA11.
For cycles that are not targeted to system memory
or internal I/O, MA11–MA0 are used to provide non-
multiplexed ISA-type address signals SA23–SA12,
,
CAS0H
, and
CAS0L
respectively. Each pin se-
SRCS3
Élan™SC310 Microcontroller Data Sheet
–
SRCS0
P R E L I M I N A R Y
, see
MWE
Write Enable (Output; Active Low)
Write Enable is the write command strobe for the
DRAM and SRAM devices.
RAS1–RAS0
Row Address Strobe (Output; Active Low)
Row Address Strobe indicates to DRAM that a valid
row address is present on the MA11–MA0 lines. One
RAS signal is allocated for each DRAM bank, one per
word.
ROMCS
BIOS ROM Chip Select (Output; Active Low)
BIOS ROM Chip Select is an active Low output that
provides the chip select function for the Flash/ROM ar-
ray. ROMCS is used to select the BIOS ROM, and can
be configured to respond to direct addressing or MMS
addressing. When configured for direct addressing, the
BIOS ROM can reside at one or all of the following ad-
dress ranges:
The BIOS ROM chip select is also active for accesses
into the 64K segment that contains the boot vector, at
address FF0000h to FFFFFFh.
For more information about the
Using 16-Bit
ÉlanSC310 Microcontrollers Application Note , order
#21825.
MA 11 10
SA
Power management interface
Miscellaneous interface
Local bus interface
Maximum ISA bus interface
JTAG-boundary scan interface
Reset and power
as shown in Table 11. See also SA11–SA0 on
page 32.
Table 11. Non-Multiplexed Address Signals
12 13 23 22 21 20 19 18 17 16 15 14
ROMCS
Provided by MA11–MA0
9
0F0000h–0FFFFFh
0E0000h–0EFFFFh
0D0000h–0DFFFFh
0C0000h–0CFFFFh
0A0000h–0AFFFFh
8
Designs in Élan
7
6
5
ROMCS
4
3
TM
pin, see the
SC300 and
2
1
0