ELANSC310 AMD [Advanced Micro Devices], ELANSC310 Datasheet - Page 50

• Manufacturer Part Number: ELANSC310
• Description: Single-Chip, 32-Bit, PC/AT Microcontroller
• Manufacturer: AMD [Advanced Micro Devices]

PGP Pins
PGP2 and PGP3 can be programmed to be set to a
pre-defined state for Micro Power Off mode. For more
information, see the Élan
grammer’s Reference Manual , order # 20665.
Micro Power Off Mode Implementation
The system should not be powered up directly into
Micro Power Off mode. The system must be allowed to
fully power up into High Speed mode upon initial power
application of any power source. If a battery has insuf-
ficient power for the ÉlanSC310 microcontroller to ini-
tialize into High Speed mode, the system design must
first power up the ÉlanSC310 microcontroller from the
main source, and not allow the chip to be powered from
the battery until after it is fully initialized in High Speed
mode and properly transitioned into Micro Power Off
mode.
This requirement presents an issue when using (for ex-
ample) a 3 V Lithium battery cell as a back-up power
source to prevent the RTC from losing its contents dur-
ing Micro Power Off mode. If the battery is installed be-
fore any other power sour ce is available, the
requirement cannot be met because such a small bat-
tery is incapable of supplying sufficient power to fully
initialize the system. The ÉlanSC310 microcontroller
comes up in an undefined state, perhaps drawing suf-
ficient current to drain the battery.
The ÉlanSC310 microcontroller backup power source
should be installed only after the system is powered by
the main power source prior to a transition into Micro
Power Off mode. When the system has transitioned
into Micro Power Off mode properly, the simultaneous
benefits of low power consumption while maintaining
RTC data such as time, date, and system configuration
can be realized.
Note: The timing sequence and specifications for
power-up, entering, and exiting Micro Power Off mode
must be met. The timing information begins on
page 88.
50
IORESET
0
0
1
1
RESIN
0
1
0
1
TM
SC310 Microcontroller Pro-
Élan™SC310 Microcontroller Data Sheet
Force Term
Table 23. Internal I/O Pulldown States
Inactive
Active
Active
Active
P R E L I M I N A R Y
This condition occurs when any power source is initially turned on. The
ÉlanSC310 microcontroller’s core and analog VCC is transitioning to
on and RESIN is active (the initial power-up state). See “Micro Power
Off Mode” on page 46 for more details.
This condition occurs when the core and analog VCC is stable, the
RESIN pin has been inactive, and the primary power supply outputs
are off (the normal Micro Power Off state).
This condition should be treated as condition 0,0 above.
This occurs when the secondary power supply is on, the RESIN input
is inactive, and the primary power supply is on and has deasserted
IORESET (normal system operating state).
For more information about Micro Power Off mode im-
plementation, see the Élan
Microcontrollers Solution For Systems Using a Back-
up Battery Application Note , order #20746 and the
Troubleshooting Guide for Micro Power Off Mode on
Élan
Evaluation Boards Application Note , order #21810.
Core Peripheral Controllers
The ÉlanSC310 microcontroller includes all the stan-
dard peripheral controllers that make up a PC/AT sys-
tem, including interrupt controller, DMA controller,
counter/timer, and ISA bus controller. For more infor-
mation, see Chapter 3 of the Élan
troller Programmer’s Reference Manual , order #20665.
Interrupt Controller
The ÉlanSC310 microcontroller interrupt controller is
functionally compatible with the standard cascaded
8259A controller pair as implemented in the PC/AT.
The interrupt controller block accepts requests from
peripherals, resolves priority on pending interrupts and
interrupts in service, issues an interrupt request to the
processor, and provides the interrupt vector to the
processor.
The two devices are internally connected and must be
programmed to operate in Cascade mode for operation
of all 15 interrupt channels. Interrupt controller 1 occu-
pies I/O addresses 020h–021h and is configured for
master operation in Cascade mode. Interrupt controller
2 occupies I/O addresses 0A0h–0A1h and is config-
ured for slave operation. Channel 2 (IRQ2) of interrupt
controller 1 is used for cascading and is not available
externally.
The output of Timer 0 in the counter/timer section is
connected to Channel 0 (IRQ0) of Interrupt controller 1.
IRQ0 can be programmed to generate an SMI. See
Chapter 1 of the Élan
grammer’s Reference Manual , order #20665. Interrupt
request from the Real-Time Clock is connected to
Channel 0 (IRQ8) of Interrupt Controller 2. IRQ13 is re-
TM
SC300 and ÉlanSC310 Microcontrollers and
Comments
TM
SC310 Microcontroller Pro-
TM
SC300 and Élan
TM
SC310 Microcon-
TM
SC310