ELANSC310 AMD [Advanced Micro Devices], ELANSC310 Datasheet - Page 49

• Manufacturer Part Number: ELANSC310
• Description: Single-Chip, 32-Bit, PC/AT Microcontroller
• Manufacturer: AMD [Advanced Micro Devices]

The Micro Power Refresh bit will always be cleared
whenever the RESIN input is sampled Low. Therefore,
when the core is initially powered up, the Micro Power
DRAM refresh feature will be disabled. This bit is unaf-
fected by the IORESET input. This bit will provide the
system BIOS with a mechanism to determine whether
or not the system DRAM data has been retained after
a reset (IORESET) has occurred.
If Self-Refresh mode is selected and enabled for Micro
Power Off mode, then when Micro Power Off mode is
exited, the ÉlanSC310 microcontroller will properly
force a CAS-before-RAS refresh cycle to cause the
DRAMs to exit the Self-Refresh mode. The ÉlanSC310
microcontroller then transitions to the normal CAS-be-
fore-RAS refresh mode. This functionality is exactly the
same as the Self-Refresh mode exit when the CPU
Clock Stopped mode is exited. The ÉlanSC310 micro-
controller generates one CAS-before-RAS refresh
cycle to force the DRAM to exit the Self-Refresh mode.
This is also true for the Micro Power DRAM refresh fea-
ture.
The timing diagrams in Figure 34 and Figure 35 on
page 91 show the sequence required to guarantee a
proper transition into the Micro Power state. This se-
quence is especially critical when the DRAM refresh
option is selected. Note that the power pins of the
ÉlanSC310 microcontroller must be kept stable for
some time after the IORESET input has gone active.
“Stable” means that these power pins should remain at
least at their VCC (min) value for the specified time in-
dicated in Table 45 on page 88.
RESIN and IORESET
The ÉlanSC310 microcontroller has two reset inputs to
support the Micro Power Off mode. These two inputs
are RESIN and IORESET. If Micro Power Off mode is
not to be used, the system designer should drive these
two inputs from a common power-on reset source.
Note that the RESIN signal is a 3.3-V only input and is
not 5-V safe. For more details, see Table 23 on page
50.
RSTDRV Signal Timing
RSTDRV is High True output of the ÉlanSC310 micro-
controller and is a function of the internal core’s reset
state, the state of the
the value for the PLL start-up timer in the Clock Control
Register (Index 8Fh). (For more information, see “Loop
Filters” on page 86.) RSTDRV indicates that the PLLs
are gated off from the core and prevents the CPU from
executing instructions until the PLL outputs have stabi-
lized.
RSTDRV is asserted immediately whenever VCC
power is applied and either
serted. The pulse width of RSTDRV may vary and is
determined by the PLL start-up timer and whether or
RESIN
and
RESIN
IORESET
Élan™SC310 Microcontroller Data Sheet
or
IORESET
signals, and
P R E L I M I N A R Y
is as-
not
versus warm reset or Micro Power Off mode exit).
On a cold boot, when
applied to the VCC inputs and then deasserted after
time delay (t1), the RSTDRV is immediately asserted
when power is applied, and then held True until
and
RESIN
to their default values, the PLL start-up time value in
the Clock Control Register is set to 4 ms and is insuffi-
cient time for the PLLs to start up. This is why the VCC-
to-RESIN timing specification (t1) of 1 second is re-
quired to allow sufficient time for the crystal and the
PLLs to power up and stabilize before
SET
On a warm reset, the power stays on and the VCC in-
puts are already powered up while the PLLs are either
powered and running or gated off. RSTDRV is asserted
quickly after
also determined by the
default PLL start-up timer has a value of 4 ms. It is
therefore recommended that the system design guar-
antees at least a minimum
for warm resets.
On a wake-up from Micro Power Off mode, VCC and
AVCC power to the core is maintained active, and the
Clock Configuration Register value for the PLL start-up
timer is preserved, but power is removed from all the
other VCC inputs, and the PLLs are gated off. RSTDRV
is asserted internally and the output is driven active as
soon as VSYS is powered up. When
asserted to go into Micro Power Off mode, RSTDRV is
immediately asserted igh. When power is removed
from the VSYS input (which is also VCCIO for RST-
DRV), the voltage level of RSTDRV begins to decay at
the same rate as VSYS until it reaches around 0.7 V,
where it remains while in Micro Power Off mode. This
indicates that RSTDRV is still asserted internally inside
the microcontroller and is attempting to drive the exter-
nal pin High, but is unable to without power applied to
its I/O driver. When exiting Micro Power Off mode, as
soon as VSYS is powered up, RSTDRV is immediately
driven High and will remain High until the
nal is de-asserted and the preserved programmed
value in the PLL start-up timer has expired.
Force Term
Figure 4 on page 48 and Table 23 on page 50 show the
function of the IORESET,
When in Micro Power Off mode, it is important not to
back power any of the powered-off internal power
planes. Table 2–Table 10 show the VCCIO and VCC
clamp voltage sources for each signal pin. Ensure that
all signals, which are either driven by (VCCIO) or
clamped to (VCC Clamp) a powered-off voltage
source, are also either powered off or driven Low.
IORESET
IORESET
allow RSTDRV to be deasserted.
causes all the configuration registers to be reset
and/or
RESIN
are deasserted. Because the assertion of
RESIN
is asserted, with the pulse width
RESIN
RESIN
RESIN
is deasserted (i.e., cold boot
RESIN
is asserted while power is
pulse width, because the
pulse width of 250 ms
, and Force Term.
RESIN
IORESET
IORESET
and
RESIN
is first
IORE-
sig-
49