U3741BM-M2FLG3 TEMIC [TEMIC Semiconductors], U3741BM-M2FLG3 Datasheet - Page 10

• Manufacturer Part Number: U3741BM-M2FLG3
• Description: UHF ASK/FSK Receiver
• Manufacturer: TEMIC [TEMIC Semiconductors]

Bitcheck Mode
In bitcheck mode the incoming data stream is examined
to distinguish between a valid signal from a correspond-
ing transmitter and signals due to noise. This is done by
subsequent time frame checks where the distances
between 2 signal edges are continuously compared to a
programmable time window. The maximum count of this
edge-to-edge tests before the receiver switches to
receiving mode is also programmable.
Configuring the bitcheck
Assuming a modulation scheme that contains 2 edges per
bit, two time frame checks are verifying one bit. This is
valid for Manchester, Bi-phase and most other
modulation schemes. The maximum count of bits to be
checked can be set to 0, 3, 6 or 9 bits via the variable
N
and 18 edge to edge checks respectively. If N
to a higher value, the receiver is less likely to switch to
receiving mode due to noise. In the presence of a valid
transmitter signal, the bitcheck takes less time if N
is set to a lower value. In polling mode, the bitcheck time
is not dependent on N
example where 3 bits are tested successfully and the data
signal is transferred to Pin DATA.
According to figure 12, the time window for the bitcheck
is defined by two separate time limits. If the edge-to-edge
time t
and the upper bitcheck limit T
continued. If t
T
switches to sleep mode.
U3741BM
10 (25)
Lim_max
Dem_out
Bitcheck
ee
( Lim_min = 14, Lim_max = 24 )
Enable IC
Bitcheck
Dem_out
Bitcheck–Counter
is in between the lower bitcheck limit T
Figure 12. Valid time window for bitcheck
, the bitcheck will be terminated and the receiver
in the OPMODE register. This implies 0, 6, 12
ee
is smaller than T
T
T
Lim_max
Lim_min
t
ee
T
Startup
0
Bitcheck
1/f
Sig
Lim_max
. Figure 11 shows an
1
Lim_min
2 3 4 5 6
Preliminary Information
, the check will be
Figure 13. Timing diagram during bitcheck
T
Clk
or t
Bitcheck
7 8 1
ee
exceeds
Lim_min
Bitcheck
2
is set
3
4 5
6 7 8 9
1/2 Bit
For best noise immunity it is recommended to use a low
span between T
using a fixed frequency at a 50% duty cycle for the
transmitter preburst. A ‘11111...’ or a ‘10101...’ sequence
in Manchester or Bi-phase is a good choice concerning
that advice. A good compromise between receiver
sensitivity and susceptibility to noise is a time window of
Using pre-burst patterns that contain various edge-to-
edge time periods, the bitcheck limits must be
programmed according to the required span.
The bitcheck limits are determined by means of the
formula below.
T
T
Lim_min and Lim_max are defined by a 5-bit word each
within the LIMIT register.
Using above formulas Lim_min and Lim_max can be
determined according to the required T
and T
T
(t
chapter ‘Receiving Mode’. Due to this, the lower limit
should be set to Lim_min
the upper limit is Lim_max = 63.
Figures 13, 14 and 15 are illustrating the bitcheck
for the default bitcheck limits Lim_min = 14 and
Lim_max = 24. When the IC is enabled, the signal
processing circuits are enabled during T
of the ASK/ FSK demodulator (Dem_out) is undefined
during that period. When the bitcheck becomes active,
the bitcheck counter is clocked with the cycle T
Figure 13 shows how the bitcheck proceeds if the bit-
check counter value CV_Lim is within the limits defined
by Lim_min and Lim_max at the occurrence of a signal
edge. In figure 14 the bitcheck fails as the value CV_lim
is lower than the limit Lim_min. The bitcheck also fails
if CV_Lim reaches Lim_max. This is illustrated in
figure 15.
Lim_min
Lim_max
Lim_max
DATA_L_min
25% regarding the expected edge-to-edge time t
10
11 12 13 14
XClk
= Lim_min
= (Lim_max –1) T
. The time resolution in defining T
is T
15 16 17 18
, t
Bitcheck ok
XClk
DATA_H_min
Lim_min
. The minimum edge-to-edge time t
1 2 3 4 5 6
T
and T
XClk
) is defined according to the
10. The maximum value of
XClk
Lim_max
1/2 Bit
7 8 9 10 11 12 13 14 15
Rev. A1, 15-Oct-98
. This is achieved
Lim_min
Startup
Bitcheck ok
. The output
Lim_min
, T
1 2 3 4
XClk
1/2 Bit
Lim_max
.
and
ee
ee
.