U3741BM-M2FLG3 TEMIC [TEMIC Semiconductors], U3741BM-M2FLG3 Datasheet - Page 11

• Manufacturer Part Number: U3741BM-M2FLG3
• Description: UHF ASK/FSK Receiver
• Manufacturer: TEMIC [TEMIC Semiconductors]

Rev. A1, 15-Oct-98
Duration of the Bitcheck
If no transmitter signal is present during the bitcheck, the
output of the ASK/ FSK demodulator delivers random
signals. The bitcheck is a statistical process and T
varies for each check. Therefore, an average value for
T
T
T
T
polling mode.
In the presence of a valid transmitter signal, T
dependant on the frequency of that signal, f
count of the checked bits, N
N
requiring a higher value for the transmitter pre-burst
T
Receiving Mode
If the bitcheck is successful for all bits specified by
N
According to figure 11, the internal data signal is
switched to Pin DATA in that case. A connected C can
be woken up by the negative edge at Pin DATA. The
receiver stays in that condition until it is switched back to
polling mode explicitly.
Bitcheck
Bitcheck
Clk
Bitcheck
Preburst
Bitcheck
Bitcheck
. A higher baudrate range causes a lower value for
( Lim_min = 14, Lim_max = 24 )
Enable IC
Bitcheck
Dem_out
Bitcheck–Counter
( Lim_min = 14, Lim_max = 24 )
Enable IC
Bitcheck
Dem_out
Bitcheck–Counter
.
, the receiver switches to receiving mode.
depends on the selected baudrate range and on
resulting in a lower current consumption for
thereby results in a longer period for T
is given in the electrical characteristics.
Startup – Mode
Startup – Mode
Figure 15. Timing diagram for failed bitcheck (condition: CV_Lim < Lim_max)
Figure 14. Timing diagram for failed bitcheck (condition: CV_Lim < Lim_min)
0
0
Bitcheck
1
1
2 3 4 5 6
2 3 4 5 6
. A higher value for
Preliminary Information
1
7
Sig
Bitcheck – Mode
2
1
Bitcheck
3
2
and the
4 5
Bitcheck
Bitcheck
3
4 5
1/2 Bit
Bitcheck – Mode
6 7 8 9
6 7 8 9
is
Bitcheck failed ( CV_Lim < Lim_min )
10
Digital Signal Processing
The data from the ASK/ FSK demodulator (Dem_out) is
digitally processed in different ways and as a result
converted into the output signal data. This processing
depends on the selected baudrate range (BR_Range).
Figure 16 illustrates how Dem_out is synchronized by the
extended clock cycle T
Bitcheck counter. Data can change its state only after
T
Data signal as a result is always an integral multiple of
T
The minimum time period between two edges of the data
signal is limited to t
efficient suppression of spikes at the DATA output. At the
same time it limits the maximum frequency of edges at
DATA. This eases the interrupt handling of a connected
edge-to-edge time interval t
If t
following level is frozen for the time period
T
bitcheck limits T
time period.
The maximum time period for DATA to be Low is limited
to T
finite response time in programming or switching off the
receiver via Pin DATA. T
than the maximum time period indicated by the
transmitter data stream. Figure 18 gives an example
where Dem_out remains Low after the receiver is in
receiving mode.
11 12
10
C. T
XClk
XClk
DATA_min
1/2 Bit
11 12
ee
DATA_L_max
DATA_min
.
13 14 15 16 17 18 19
is in between the specified bitcheck limits, the
elapsed. The edge-to-edge time period t
= tmin1, in case of t
Sleep–Mode
is to some extent affected by the preceding
0
. This function is employed to ensure a
DATA_min
Bitcheck failed ( CV_Lim = Lim_max )
20
21 22 23 24
ee
XClk
DATA_L_max
. This clock is also used for the
= tmin2 is the relevant stable
T
ee
DATA_min
U3741BM
as illustrated in figure 17.
ee
Sleep–Mode
being outside that
0
. This implies an
is thereby longer
ee
11 (25)
of the