U3741BM-M2FLG3 TEMIC [TEMIC Semiconductors], U3741BM-M2FLG3 Datasheet - Page 9

• Manufacturer Part Number: U3741BM-M2FLG3
• Description: UHF ASK/FSK Receiver
• Manufacturer: TEMIC [TEMIC Semiconductors]

Rev. A1, 15-Oct-98
NO
( Number of checked Bits: 3 )
Enable IC
Bitcheck
Dem_out
DATA
Sleep mode:
All circuits for signal processing are
disabled. Only XTO and Polling
logic is enabled.
I
T
Start-up mode:
The signal processing circuits are
enabled. After the start-up time
(T
condition and ready to receive.
I
T
Bitcheck mode:
The incomming data stream is
analyzed. If the timing indicates a
valid transmitter signal, the receiver is
set to receiving mode. Otherwise it is
set to Sleep mode.
I
T
Receiving mode:
The receiver is turned on permanently
and passes the data stream to the
connected
mode through an OFF command via
Pin DATA or ENABLE.
I
S
S
S
S
Sleep
Startup
Bitcheck
Startup
= I
= I
= I
= I
Soff
Soff
Soff
Soff
= Sleep X
) all circuits are in stable
Polling – Mode
m
C. It can be set to Sleep
OFF command
Bitcheck
OK ?
Sleep
Figure 11. Timing diagram for complete sucessful bitcheck
YES
Preliminary Information
1024
1/2 Bit
Figure 10. Polling mode flow chart
T
Clk
1/2 Bit
1/2 Bit
Sleep:
X
T
T
T
Bitcheck ok
Clk
Startup
Bitcheck:
Sleep
1/2 Bit
:
:
:
1/2 Bit
5-bit word defined by Sleep0 to
Sleep4 in OPMODE register
Extension factor defined by
XSleep
according to table 8
Basic clock cycle defined by f
and Pin MODE
Is defined by the selected baud rate
range and T
is defined by Baud0 and Baud1 in
the OPMODE register.
Depends on the result of the
bitcheck
If the bitcheck is ok, T
depends on the number of bits to be
checked (N
utilized data rate.
If the bitcheck fails, the average
time period for that check depends
on the selected baud rate range and
on T
defined by Baud0 and Baud1 in the
OPMODE register.
1/2 Bit
Clk
Std
. The baud rate range is
Receiving mode
and XSleep
Bitcheck
Clk
. The baud rate range
U3741BM
) and on the
Temp
Bitcheck
XTO
9 (25)