U3741BM-M2FLG3 TEMIC [TEMIC Semiconductors], U3741BM-M2FLG3 Datasheet - Page 13

• Manufacturer Part Number: U3741BM-M2FLG3
• Description: UHF ASK/FSK Receiver
• Manufacturer: TEMIC [TEMIC Semiconductors]

Rev. A1, 15-Oct-98
Configuration of the Receiver
The U3741BM receiver is configured via two 12-bit
RAM registers called OPMODE and LIMIT. The
registers can be programmed by means of the
bi-directional DATA port. If the register contents have
changed due to a voltage drop, this condition is indicated
by a certain output pattern called reset marker (RM). The
receiver must be reprogrammed in that case. After a
power-on reset (POR), the registers are set to default
mode. If the receiver is operated in default mode, there is
no need to program the registers.
Table 3 shows the structure of the registers. According to
table 2, bit 1 defines if the receiver is set back to polling
mode via the OFF command, (see chapter ‘Receiving
Mode’) or if it is programmed. Bit 2 represents the
register address. It selects the appropriate register to be
programmed.
Out1 (mC)
DATA (U3741BM)
Serial bi–directional
data line
ENABLE
DATA (U3741BM)
Serial bi–directional
data line
Receiver
on
X
X
X
X
Receiver on
Figure 20. Timing diagram of the OFF-command via Pin ENABLE
t1
Figure 19. Timing diagram of the OFF-command via Pin DATA
OFF Command
t2
Preliminary Information
toff
T
Doze
t3
(Startbit)
t4
Bit 1
(”1”)
t10
t5
t7
Table 2. Effect of Bit 1 and Bit 2 in programming the registers
Table 4 and the following illustrate the effect of the indi-
vidual configuration words. The default configuration is
highlighted for each word.
BR_Range sets the appropriate baud rate range. At the
same time it defines XLim. XLim is used to define the
bitcheck limits T
table 4.
POUT can be used to control the sensitivity of the
receiver. In that application, POUT is set to 1 to reduce the
sensitivity. This implies that the receiver operates with
full sensitivity after a POR.
Bit 1 Bit 2
T
Sleep
1
0
0
x
1
0
T
Sleep
The receiver is set back to polling
mode (OFF command)
The OPMODE register is programmed
The LIMIT register is programmed
Lim_min
Startup mode
and T
U3741BM
Action
X
X
Lim_max
Startup mode
as shown in
X
X
13 (25)