A43L2632V-7 AMICC [AMIC Technology], A43L2632V-7 Datasheet - Page 10

• Manufacturer Part Number: A43L2632V-7
• Description: 1M X 32 Bit X 4 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

Operating AC Parameter
(AC operating conditions unless otherwise noted)
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
PRELIMINARY
Symbol
t
t
t
t
t
t
t
t
t
RAS(max)
t
RRD(min)
RCD(min)
RAS(min)
CDL(min)
RDL(min)
BDL(min)
CCD(min)
RP(min)
RC(min)
2. Minimum delay is required to complete write.
then rounding off to the next higher integer.
Row active to row active delay
Row precharge time
Row active time
Row cycle time
Last data in new col. Address delay
Last data in row precharge
Last data in to burst stop
Col. Address to col. Address delay
RAS to
(January, 2005, Version 0.0)
CAS
Parameter
delay
9
12
15
63
12
15
42
-6
6
6
1
Version
100
15
15
15
42
65
14
-7
7
7
1
AMIC Technology, Corp.
Unit
ns
ns
ns
ns
µ s
ns
ns
ns
ns
ns
A43L2632
Note
1
1
1
1
1
2
2
2