A43L2632V-7 AMICC [AMIC Technology], A43L2632V-7 Datasheet - Page 13
A43L2632V-7
Manufacturer Part Number
A43L2632V-7
Description
1M X 32 Bit X 4 Banks Synchronous DRAM
Manufacturer
AMICC [AMIC Technology]
Datasheet
1.A43L2632V-7.pdf
(43 pages)
- Current page: 13 of 43
- Download datasheet (2Mb)
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 µ s.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Burst Sequence (Burst Length = 4)
Burst Sequence (Burst Length = 8)
PRELIMINARY
A2
Initial address
0
0
0
0
1
1
1
1
A1
Initial address
0
0
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
A0
0
1
0
1
(January, 2005, Version 0.0)
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
0
1
2
3
2
3
4
5
6
7
0
1
Sequential
3
4
5
6
7
0
1
2
1
2
3
0
Sequential
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
2
3
0
1
12
6
7
0
1
2
3
4
5
3
0
1
2
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
AMIC Technology, Corp.
1
0
3
2
Interleave
3
2
1
0
7
6
5
4
Interleave
4
5
6
7
0
1
2
3
2
3
0
1
5
4
7
6
1
0
3
2
A43L2632
6
7
4
5
2
3
0
1
3
2
1
0
7
6
5
4
3
2
1
0
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