MSP3415G ETC, MSP3415G Datasheet - Page 16

• Manufacturer Part Number: MSP3415G
• Description: MSP 34x5G Multistandard Sound Processor Family
• Manufacturer: ETC

MSP 34x5G
3.1.2. Description of CONTROL Register
Table 3–3: CONTROL as a Write Register
Table 3–4: CONTROL as a Read Register
3.1.3. Protocol Description
Write to DSP or Demodulator
Read from DSP or Demodulator
Write to Control Register
Read from Control Register
Note: S =
16
S
S
S
S
Name
CONTROL
Name
CONTROL
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on,
read once to be reset.
address
address
address
address
device
device
device
device
write
write
write
write
P =
ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray)
NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’
Wait = I
Wait ACK sub-addr ACK addr-byte
Wait ACK sub-addr ACK addr-byte
Wait ACK sub-addr ACK data-byte
Wait ACK
I
I
or from MSP indicating internal error state
This waiting time is max. 1 ms
2
2
2
Subaddress
00
Subaddress
00
C-Bus Start Condition from master
C-Bus Stop Condition from master
C-Clock line is held low, while the MSP is processing the I
hex
hex
00hex
Bit[15] (MSB)
1 : RESET
0 : normal
RESET status after last reading of
CONTROL:
0 : no reset occured
1 : reset occured
ACK S
high
high
high
address
device
read
ACK addr-byte
ACK addr-byte
ACK data-byte
Wait
low
low
low
ACK data-byte-
ACK data-byte
ACK S
ACK P
high
high
address
device
ACK data-byte
read
ACK data-byte
bit[15] of CONTROL
2
Bits[14:0]
0
Bit
Internal hardware status:
0 : no error occured
1 : internal error occured
C command.
low
Wait
low
ACK data-byte-
NAK P
ACK P
PRELIMINARY DATA SHEET
high
will be set; it must be
ACK data-byte
Bit
not of interest
low
Micronas
NAK P