HY5PS1G421LM HYNIX [Hynix Semiconductor], HY5PS1G421LM Datasheet - Page 10
HY5PS1G421LM
Manufacturer Part Number
HY5PS1G421LM
Description
1Gb DDR2 SDRAM(DDP)
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
1.HY5PS1G421LM.pdf
(79 pages)
- Current page: 10 of 79
- Download datasheet (6Mb)
Rev. 0.2 / Oct. 2005
2. Functional Description
2.1 Simplified State Diagram
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions
and the commands to control them, not all details. In particular situations involving more than one bank,
enabling/disabling on-die termination, Power Down enty/exit - among other things - are not captured
in full detail.
Write
calibration
Autoprecharge
Setting
EMRS
MRS
WRA
OCD
CKEL
Writing
with
Writing
Power
Active
Down
CKEL
Write
CKEL
MRS
CKEH
PR, PRA
PR
WRA
Precharging
precharged
Initialization
Activating
Sequence
All banks
PR, PRA
Active
Bank
Idle
ACT
Read
RDA
PR, PRA
RDA
SRF
CKEH
CKEL
Read
CKEH
Refreshing
REF
Autoprecharge
Self
Precharge
Reading
Power
CKEL
Reading
Down
CKEL
with
CKEL = CKE low, enter Power Down
CKEH = CKE high, exit Power Down, exit Self Refresh
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
PR(A) = Precharge (All)
MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Refresh
RDA
Read
CKEL
Refreshing
1HY5PS12421(L)M
HY5PS12821(L)M
Command Sequence
Automatic Sequence
10
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