HY5PS1G421LM HYNIX [Hynix Semiconductor], HY5PS1G421LM Datasheet - Page 49

• Manufacturer Part Number: HY5PS1G421LM
• Description: 1Gb DDR2 SDRAM(DDP)
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 0.2 / Oct. 2005
2.9 Power-Down
Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE
is not allowed to go low while mode register or extended mode register command time, or read or write operation
is in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto-
precharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those opera-
tions. Timing diagrams are shown in the following pages with details for entry into power down.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting
power-down mode for proper read operation.
If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down
occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon
entering precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit
active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of
the DDR2 SDRAM, and ODT should be in a valid state but all other input signals are “Don’t Care”. CKE low must
be maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect com-
mand). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied
with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined
at AC spec table of this data sheet.
Basic Power Down Entry and Exit timing diagram
Command
CK/CK
CKE
t
VALID
IS
t
IH
Enter Power-Down mode
t
CKE
t
IS
NOP
t
IH
t
CKE
t
IH
Exit Power-Down mode
t
IS
NOP
t
t
XP,
XARDS
t
XARD,
VALID
t
CKE
1HY5PS12421(L)M
HY5PS12821(L)M
VALID
t
IH
t
IS
VALID
t
IH
Don’t Care
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