HY5PS1G421LM HYNIX [Hynix Semiconductor], HY5PS1G421LM Datasheet - Page 34

• Manufacturer Part Number: HY5PS1G421LM
• Description: 1Gb DDR2 SDRAM(DDP)
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 0.2 / Oct. 2005
Burst Write followed by Burst Read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4
The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 +
tWTR]. This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from
the input buffer into sense amplifiers in the array. tWTR is defined in AC spec table of this data sheet.
Burst Write Operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4
CMD
CK/CK
DQS/
DQS
DQ
CMD
CK/CK
DQS/
DQS
DQs
T0
NOP
WRITE A
T0
WL = RL - 1 = 4
WL = RL - 1 = 2
T1
Write to Read = CL - 1 + BL/2 + tWTR
NOP
T1
DQS
DQS
NOP
T2
DIN A
NOP
T2
< = t
0
DIN A
NOP
0
DQSS
DIN A
1
DIN A
1
T3
DIN A
NOP
T3
2
NOP
DIN A
2
DIN A
3
DIN A
Post CAS
3
READ A
T4
T4
NOP
Completion of
the Burst Write
> = tWTR
AL = 2
T5
NOP
T5
NOP
> = WR
T6
Precharge
NOP
T6
RL =5
1HY5PS12421(L)M
HY5PS12821(L)M
T7
NOP
CL = 3
T7
NOP
> = tRP
T8
NOP
Tn
Activate
Bank A
T9
34
DOUT A
0