HY5PS1G421LM HYNIX [Hynix Semiconductor], HY5PS1G421LM Datasheet - Page 71

• Manufacturer Part Number: HY5PS1G421LM
• Description: 1Gb DDR2 SDRAM(DDP)
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 0.2 / Oct. 2005
For purposes of IDD testing, the following parameters are to be utilized
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum t RC(IDD) without violating t RRD(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 4/4/4: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D
-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
-DDR2-533 5/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
t RFC(IDD)-512Mb
t RRD(IDD)-x4/x8
t RRD(IDD)-x16
t RASmax(IDD)
t RASmin(IDD)
Parameter
t RCD(IDD)
t RC(IDD)
t CK(IDD)
t RP(IDD)
CL(IDD)
70000
5-5-5
105
7.5
15
60
45
15
5
9
3
DDR2-667
70000
6-6-6
105
7.5
18
63
45
18
6
9
3
70000
4-4-4
3.75
105
7.5
15
60
10
45
15
4
DDR2-533
70000
18.75
63.75
18.75
5-5-5
3.75
105
7.5
10
45
5
70000
3-3-3
105
7.5
15
55
10
40
15
3
5
1HY5PS12421(L)M
DDR2-400
HY5PS12821(L)M
70000
4-4-4
105
7.5
20
65
10
45
20
4
5
Units
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
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