HY5PS1G421LM HYNIX [Hynix Semiconductor], HY5PS1G421LM Datasheet - Page 31
HY5PS1G421LM
Manufacturer Part Number
HY5PS1G421LM
Description
1Gb DDR2 SDRAM(DDP)
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
1.HY5PS1G421LM.pdf
(79 pages)
- Current page: 31 of 79
- Download datasheet (6Mb)
Rev. 0.2 / Oct. 2005
Seamless Burst Read Operation: RL = 5, AL = 2, and CL = 3, BL = 4
The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4
operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different
banks as long as the banks are activated.
CK/CK
CMD
DQS/DQS
DQs
Post CAS
T0
READ A
T1
AL = 2
NOP
Post CAS
T2
READ B
RL = 5
T3
NOP
CL =3
T4
NOP
T5
NOP
DOUT A
0
DOUT A
T6
1
NOP
DOUT A
1HY5PS12421(L)M
2
HY5PS12821(L)M
DOUT A
T7
3
NOP
DOUT B
0
DOUT B
T8
1
NOP
DOUT B
2
31
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