AX88850 ASIX [ASIX Electronics Corporation], AX88850 Datasheet - Page 14
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AX88850
Manufacturer Part Number
AX88850
Description
100BASE-TX/FX Repeater Controller
Manufacturer
ASIX [ASIX Electronics Corporation]
Datasheet
1.AX88850.pdf
(39 pages)
2.2 MII interface ( two individual MII ports )
TX_ER
(share)
TXD[3:0]
(share)
TX_EN[0]
TX_EN[1]
RXD[0][3:0]
RXD[1][3:0]
RX_ER[0]
RX_ER[1]
RX_CLK[0]
RX_CLK[1]
RX_DV[0]
RX_DV[1]
CRS[0]
CRS[1]
COL
(share)
OPT0
OPT1
Signal Name Type Pin No.
AX88850
O/ML
O/ML
O/ML
I/PU
I/PU
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
I/PU
I/PU
O/L
O/L
I
I
102-99
97-94
86-83
104
105
106
107
108
92
82
98
87
88
89
90
91
81
Transmit Error : TX_ER is transition synchronously with respect to the rising
edge of TX_CLK . Asserted high when a code violation is request to be send
Transmit Data : TXD[3:0] is transition synchronously with respect to the
rising edge of TX_CLK. For each TX_CLK period in which TX_EN is
asserted, TXD[3:0] are accepted for transmission by the PHY.
Transmit Enable : TX_EN is transition synchronously with respect to the
rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles
on TXD [3:0] for transmission.
Receive Data : RXD [3:0] is driven by the PHY synchronously with respect to
RX_CLK.
Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK, is
asserted for one or more RX_CLK periods to indicate to the port that an error
has detected.
Receive Clock : RX_CLK is a continuous clock that provides the timing
reference for the transfer of the RX_DV,RXD [3:0] and RX_ER signals from
the PHY to the MII port of the repeater.
Receive Data Valid : RX_DV is driven by the PHY synchronously with
respect to RX_CLK. Asserted high when valid data is present on RXD [3:1].
Carrier Sense : Asynchronous signal CRS is asserted by the PHY when either
the transmit or receive medium is non-idle.
Collision Signal :This pin indicates collision(s) , that occurred at the collision
domain of the hub, to MII interface devices. Both the MII port use this signal
commonly.
Option for external device type : Default ‘high’ is for PHY type device.
Otherwise, ‘low’ for MAC type device.
14
Description
ASIX ELECTRONICS CORPORATION
PRELIMINARY