AX88850 ASIX [ASIX Electronics Corporation], AX88850 Datasheet - Page 22

• Manufacturer Part Number: AX88850
• Description: 100BASE-TX/FX Repeater Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

3.8 Management Counters
There are four management counters in each port. These 16-bit-wide management counters keep track of the
following events:
Collision Event Counter
It indicates the number of times that collision occurrences on a port.
Partition Event Counter
It indicates the number of times that a port has been partition.
Short Event Counter
It indicates the number of packets that is shorter than 76 BT.
Late Event Counter
It indicates the number of collision occurrences time after 512 BT when carrier presents.
Fault Carrier Event Counter (AX88853 only)
It indicates the number of times that fault carrier occurrences on a port.
These counters can be read out by MIB serial access interface and will be clear after read operation.
3.9 Station Management Access Interface
The AX88850 provides 128 registers held in 4 pages of 32(Page 0 ~ 3 Register).These registers are 16 bits wide. Only
one register of one page can be access at the same time through the MII serial
reset, Page 0 Register is the default setting. Change the value of PAGE REGISTER which exists in all pages, then
switches to any page. For example: Page 3 Register can be accessed by writing 03h to the PAGE REGISTER.
AX88850 can thus be managed through SMDC and SMDIO pins. The SMDC clock with maximum 2.5M Hz is used
to sample data train on SMDIO. The interface follows the serial management protocol defined by IEEE 802.3u clause
22.
For the protocol to work, all serial data must be “synchronized” to incoming data. To ensure data locked, a preamble
of 32 consecutive 1‘s present before the start code, then the receive logic know the beginning of the data frame.
With the setting of PHY_ACCESS = 1(stored in CONFIGURATION REGISTER), the target access device may be
physical layer devices. In this mode, SMDIO is gated to BSMDIO. SMDIO and BSMDIO must turn on in the
appropriate direction for read/write access. In the cascade system, only one
PHY_ACCESS at a time to avoid contention problems.
3.10 RID Receive-Transmit Interface(Daisy Chain Logic)
In the cascade system, repeater ID of each chip will be re-arranged by serial in/out daisy chain logic. The DAISY_IN
pin always monitor RID of the previous chained chip, and the value of (RID+1) will override the original RID of the
current chip. Then the DAISY_OUT pin will periodically (about 200us) send out the exact RID of current chip to
inform the next chained chip. By this way, each repeater chip in 8 AX88850 hub (maximum application) will keep
unique ID of itself. The RID is used in inter repeater bus arbitration and uniquely identify station management
accesses.
In this way, repeater ID won‘t be confused with PHY device ID during station management access.
Note that only RID[2:0] can be changed and RID[4:3] must be the same value for all repeaters in the cascade system.
WRITE
READ
AX88850
PREAM START OPCODE DEV_AD REG_AD
1.......1
1.......1
01
01
10
01
Management frame format
AAAAA
AAAAA
RRRRR
RRRRR
22
TA
Z0
10
ASIX ELECTRONICS CORPORATION
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
repeater
management bus. After power on
DATA
PRELIMINARY
chip
has
the
IDLE
set
Z
Z
of